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    SPLIT GATE NANOCRYSTAL MEMORY INTEGRATION
    1.
    发明申请
    SPLIT GATE NANOCRYSTAL MEMORY INTEGRATION 有权
    分割门纳米晶体存储器集成

    公开(公告)号：US20150348786A1

    公开(公告)日：2015-12-03

    申请号：US14291359

    申请日：2014-05-30

    申请人： KONSTANTIN V. LOIKO ,  BRIAN A. WINSTEAD

    发明人： KONSTANTIN V. LOIKO ,  BRIAN A. WINSTEAD

    IPC分类号： H01L21/28 ,  H01L29/792 ,  H01L29/788

    CPC分类号： H01L21/28008 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7883 ,  H01L29/792

    摘要： A method of making a split gate non-volatile memory (NVM) includes forming a charge storage layer on the substrate, depositing a first conductive layer, and depositing a capping layer. These layers are patterned to form a control gate stack. A second conductive layer is deposited over the substrate and is patterned to leave a first portion of the second conductive layer over a portion of the control gate stack and adjacent to a first side of the control gate stack. The first portion of the second conductive layer and the control gate stack are planarized to leave a dummy select gate from the first portion of the second conductive layer, where a top surface of a remaining portion of the first conductive layer is lower relative to a top surface of the dummy select gate. The dummy select gate is replaced with a select gate including metal.

    摘要翻译： 一种制造分离栅极非易失性存储器（NVM）的方法包括在衬底上形成电荷存储层，沉积第一导电层和沉积覆盖层。 将这些层图案化以形成控制栅叠层。 第二导电层沉积在衬底上并被图案化以将第二导电层的第一部分留在控制栅极堆叠的一部分上并且邻近控制栅极堆叠的第一侧。 第二导电层和控制栅极堆叠的第一部分被平坦化以从第二导电层的第一部分留出虚拟选择栅极，其中第一导电层的剩余部分的顶表面相对于顶部 虚拟选通门的表面。 虚拟选择栅极被包括金属的选择栅极替代。

    SPLIT GATE NON-VOLATILE MEMORY CELL
    4.
    发明申请
    SPLIT GATE NON-VOLATILE MEMORY CELL 有权
    分离门非挥发性记忆细胞

    公开(公告)号：US20150035034A1

    公开(公告)日：2015-02-05

    申请号：US13954205

    申请日：2013-07-30

    申请人： BRIAN A. WINSTEAD ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Jane A. Yater

    发明人： BRIAN A. WINSTEAD ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Jane A. Yater

    IPC分类号： H01L29/66 ,  H01L29/792

    CPC分类号： H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

    摘要： A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.

    摘要翻译： 制造半导体结构的方法使用具有第一类型的背景掺杂的衬底。 栅极结构在衬底上具有栅极电介质，栅极电介质上具有选择栅极层。 使用第二类型的掺杂剂，将与第一端相邻的衬底的第一部分进行植入。 在将任何掺杂剂注入到成为第二类型的第一掺杂区域的第一部分的背景掺杂之前，注入之前。 NVM栅极结构具有选择栅极，在第一掺杂区域上具有第一部分的存储层以及存储层上的控制栅极。 以与第一类型的掺杂剂非垂直的角度植入在选择栅极下形成深掺杂区域。 与第二种类型的掺杂剂一起植入形成源/漏扩展。

    ONE TRANSISTOR DRAM CELL STRUCTURE AND METHOD FOR FORMING
    5.
    发明申请
    ONE TRANSISTOR DRAM CELL STRUCTURE AND METHOD FOR FORMING 有权
    一种晶体管DRAM单元结构和形成方法

    公开(公告)号：US20100001326A1

    公开(公告)日：2010-01-07

    申请号：US12558284

    申请日：2009-09-11

    申请人： JAMES D. BURNETT ,  BRIAN A. WINSTEAD

    发明人： JAMES D. BURNETT ,  BRIAN A. WINSTEAD

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10844 ,  H01L29/7839 ,  H01L29/7841

    摘要： A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region.

    摘要翻译： 单晶体管动态随机存取存储器（DRAM）单元包括晶体管，其具有第一源极/漏极区域，第二源极/漏极区域，第一和第二源极/漏极区域之间的主体区域以及在主体上的栅极 地区。 第一源极/漏极区域包括与主体区域的肖特基二极管结，并且第二源极/漏极区域包括与身体区域的n-p二极管结。

    SPLIT GATE MEMORY CELL WITH IMPROVED ERASE PERFORMANCE
    6.
    发明申请
    SPLIT GATE MEMORY CELL WITH IMPROVED ERASE PERFORMANCE 有权
    具有改进的擦除性能的分离器门存储器单元

    公开(公告)号：US20150349142A1

    公开(公告)日：2015-12-03

    申请号：US14288975

    申请日：2014-05-28

    申请人： BRIAN A. WINSTEAD ,  Ko-Min Chang ,  Craig T. Swift

    发明人： BRIAN A. WINSTEAD ,  Ko-Min Chang ,  Craig T. Swift

    IPC分类号： H01L29/792 ,  H01L29/51 ,  H01L21/28 ,  G11C16/14

    CPC分类号： H01L21/28282 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881

    摘要： A semiconductor device includes a semiconductor substrate, a charge storage stack over a portion of the substrate. The charge storage stack includes a first dielectric layer, a layer of nanocrystals in contact with the first dielectric layer, a second dielectric layer over and in contact with the layer of nanocrystals, a nitride layer over and in contact with the second dielectric layer, and a third dielectric layer over the nitride layer.

    摘要翻译： 半导体器件包括半导体衬底，在衬底的一部分上的电荷存储堆叠。 电荷存储堆叠包括第一电介质层，与第一介电层接触的纳米晶体层，与纳米晶体层接触并与其接触的第二电介质层，在第二介电层上并与第二介电层接触的氮化物层，以及 在氮化物层上的第三电介质层。

    METHOD FOR PRECONDITIONING THIN FILM STORAGE ARRAY FOR DATA RETENTION
    7.
    发明申请
    METHOD FOR PRECONDITIONING THIN FILM STORAGE ARRAY FOR DATA RETENTION 有权
    用于预测数据保留薄膜存储阵列的方法

    公开(公告)号：US20130343112A1

    公开(公告)日：2013-12-26

    申请号：US13532973

    申请日：2012-06-26

    申请人： HORACIO P. GASQUET ,  BRIAN A. WINSTEAD

    发明人： HORACIO P. GASQUET ,  BRIAN A. WINSTEAD

    IPC分类号： G11C5/02 ,  G11C7/00 ,  G11C29/04

    CPC分类号： G11C29/06 ,  G11C16/0416 ,  G11C2216/06 ,  H01L21/28273 ,  H01L29/42332

    摘要： A method includes over-programming thin film storage (TFS) memory cells on a semiconductor wafer with a first voltage that is higher than a highest voltage used to program the memory cells during normal operation of the memory cells. With the memory cells in an over-programmed state, the wafer is exposed to a first temperature above a product specification temperature for a period of time sufficient to induce redistribution of charge among storage elements in the memory cells.

    摘要翻译： 一种方法包括在半导体晶片上超薄编程薄膜存储（TFS）存储单元，其中第一电压高于用于在存储单元的正常操作期间对存储单元进行编程的最高电压。 在存储器单元处于过度编程状态下，将晶片暴露于产品规格温度以上的第一温度足以引起存储单元中的存储元件之间的电荷重新分配的时间。

    METHOD OF MAKING A SEMICONDUCTOR STRUCTURE USEFUL IN MAKING A SPLIT GATE NON-VOLATILE MEMORY CELL
    9.
    发明申请
    METHOD OF MAKING A SEMICONDUCTOR STRUCTURE USEFUL IN MAKING A SPLIT GATE NON-VOLATILE MEMORY CELL 有权
    制造分裂栅非挥发性记忆细胞的半导体结构的方法

    公开(公告)号：US20120261769A1

    公开(公告)日：2012-10-18

    申请号：US13085533

    申请日：2011-04-13

    申请人： CHEONG M. HONG ,  BRIAN A. WINSTEAD

    发明人： CHEONG M. HONG ,  BRIAN A. WINSTEAD

    IPC分类号： H01L29/772 ,  H01L21/28

    CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/66825

    摘要： A semiconductor device comprises a semiconductor substrate and a select gate structure over a first portion of the semiconductor substrate. The select gate structure comprises a sidewall forming a corner with a second portion of the semiconductor substrate and a charge storage stack over an area comprising the second portion of the semiconductor substrate, the sidewall, and the corner. A corner portion of a top surface of the charge storage stack is non-conformal with the corner, and the corner portion of the top surface of the charge storage stack has a radius of curvature measuring approximately one-third of a thickness of the charge storage stack over the second portion of the substrate or greater. A control gate layer is formed over the charge storage stack. A portion of the control gate layer conforms to the corner portion of the top surface of the charge storage stack.

    摘要翻译： 半导体器件包括在半导体衬底的第一部分上的半导体衬底和选择栅极结构。 选择栅极结构包括形成具有半导体衬底的第二部分的角部的侧壁和在包括半导体衬底的第二部分，侧壁和角部的区域上的电荷存储堆叠。 电荷存储堆的顶表面的角部与拐角不一致，并且电荷存储堆的顶表面的角部具有测量电荷存储的厚度的约三分之一的曲率半径 堆叠在衬底的第二部分上或更大。 在电荷存储堆上形成控制栅层。 控制栅极层的一部分符合电荷存储堆的顶表面的角部。

    SEMICONDUCTOR DEVICE HAVING DIFFERENT NON-VOLATILE MEMORIES HAVING NANOCRYSTALS OF DIFFERING DENSITIES AND METHOD THEREFOR
    10.
    发明申请
    SEMICONDUCTOR DEVICE HAVING DIFFERENT NON-VOLATILE MEMORIES HAVING NANOCRYSTALS OF DIFFERING DENSITIES AND METHOD THEREFOR 有权
    具有不同浓度的纳米晶体的不同非挥发性记忆的半导体器件及其方法

    公开(公告)号：US20130193506A1

    公开(公告)日：2013-08-01

    申请号：US13362697

    申请日：2012-01-31

    申请人： SUNG-TAEG KANG ,  GOWRISHANKAR L. CHINDALORE ,  BRIAN A. WINSTEAD ,  JANE A. YATER

    发明人： SUNG-TAEG KANG ,  GOWRISHANKAR L. CHINDALORE ,  BRIAN A. WINSTEAD ,  JANE A. YATER

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42332

    摘要： A method for forming a semiconductor device includes forming a first plurality of nanocrystals over a surface of a substrate having a first region and a second region, wherein the first plurality of nanocrystals is formed in the first region and the second region and has a first density; and, after forming the first plurality of nanocrystals, forming a second plurality of nanocrystals over the surface of the substrate in the second region and not the first region, wherein the first plurality of nanocrystals together with the second plurality of nanocrystals in the second region result in a second density, wherein the second density is greater than the first density.

    摘要翻译： 一种形成半导体器件的方法包括在具有第一区域和第二区域的衬底的表面上形成第一多个纳米晶体，其中所述第一多个纳米晶体形成在所述第一区域和所述第二区域中，并具有第一密度 ; 并且在形成所述第一多个纳米晶体之后，在所述第二区域而不是所述第一区域的所述衬底的表面上形成第二多个纳米晶体，其中所述第一多个纳米晶体与所述第二区域中的所述第二多个纳米晶体结果 在第二密度中，其中第二密度大于第一密度。