公开(公告)号：US07162568B2

公开(公告)日：2007-01-09

申请号：US10757464

申请日：2004-01-15

Applicant: Chung-Ching Huang ,  Kuan-Jui Ho

Inventor： Chung-Ching Huang ,  Kuan-Jui Ho

IPC: G06F12/00

CPC classification number: G06F11/2284

Abstract: An apparatus and method of flash ROM management. The apparatus comprises a storage device, a strapping component and a process unit. The storage device stores multiple address records comprising an identity and an address range associated with a flash ROM. The strapping component is configured to output a signal to determine flash ROM type. The process unit receives a memory access request with an access range from the CPU and the signal from the strapping component queries the identity by matching the access range and the address range, and finally executes an LPC 1.1 memory access instruction with the identity and the access range corresponding to the memory cycle.

Abstract translation: 一种闪存ROM管理的设备和方法。 该装置包括存储装置，捆扎部件和处理单元。 存储设备存储包括与快闪ROM相关联的身份和地址范围的多个地址记录。 绑带组件配置为输出信号以确定闪存ROM类型。 处理单元从CPU接收具有访问范围的存储器访问请求，并且来自绑带组件的信号通过匹配访问范围和地址范围来查询身份，并且最终执行具有身份和访问权的LPC 1.1存储器访问指令 范围对应于存储器周期。

公开(公告)号：US08607084B2

公开(公告)日：2013-12-10

申请号：US13115792

申请日：2011-05-25

Applicant: Chung-Ching Huang ,  Kuo-Han Chang ,  Chih-Nan Lo ,  Donna Lim

Inventor： Chung-Ching Huang ,  Kuo-Han Chang ,  Chih-Nan Lo ,  Donna Lim

IPC: G06F1/26 ,  G06F1/00

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: A computer system and a power-management method thereof are provided. The computer system has an image-reading mode, a first power-management mode and a second power-management mode, and the computer system operating in the second power-management mode consumes less power than it consumes in the first power-management mode. The computer system comprises a first portion comprising a graphics processing unit, a memory space and a display; and a second portion comprising a storage storing an image data. When the computer system operates in the image-reading mode, the image data has been transferred to the memory space from the storage, the second portion enters to the second power-management mode from the first power-management mode, and the first portion keeps in the first power-management mode, so that the graphics processing unit can display an image by the display according to the image data stored in the memory space.

Abstract translation: 提供了一种计算机系统及其电源管理方法。 计算机系统具有图像读取模式，第一功率管理模式和第二功率管理模式，并且在第二功率管理模式下操作的计算机系统比在第一功率管理模式中消耗的功率消耗更少的功率。 计算机系统包括第一部分，包括图形处理单元，存储器空间和显示器; 以及第二部分，包括存储图像数据的存储器。 当计算机系统以图像读取模式操作时，图像数据已经从存储器传送到存储器空间，第二部分从第一电力管理模式进入第二电力管理模式，并且第一部分保持 在第一电源管理模式中，使得图形处理单元可以根据存储在存储器空间中的图像数据通过显示来显示图像。

公开(公告)号：US20100199022A1

公开(公告)日：2010-08-05

申请号：US12401133

申请日：2009-03-10

Applicant: Chun-Hsu Chen ,  Chung-Ching Huang ,  Chin-Han Chang

Inventor： Chun-Hsu Chen ,  Chung-Ching Huang ,  Chin-Han Chang

IPC: G06F12/02

CPC classification number: G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: An information access method and a computer system are provided. The computer system includes a system management bus (SMBus), a non-volatile memory, a plurality of hardware devices, a chipset, and a CPU. The hardware devices have a plurality of specific recognition information. The CPU performs a configuration process on the hardware devices through the chipset according to the standard for a SMBus protocol, so as to distribute a plurality of memory spaces in the non-volatile memory to the hardware devices. The hardware devices share the SMBus for accessing the plurality of specific recognition information in the memory spaces.

Abstract translation: 提供信息访问方法和计算机系统。 计算机系统包括系统管理总线（SMBus），非易失性存储器，多个硬件设备，芯片组和CPU。 硬件设备具有多个特定识别信息。 CPU根据SMBus协议的标准通过芯片组对硬件设备执行配置处理，以将非易失性存储器中的多个存储空间分配给硬件设备。 硬件设备共享SMBus以访问存储器空间中的多个特定识别信息。

公开(公告)号：US20070088879A1

公开(公告)日：2007-04-19

申请号：US11538693

申请日：2006-10-04

Applicant: Chung-Ching Huang ,  Ta-Chuan Liu ,  Tzu-Chiang Chiu ,  Chin-Fa Hsiao

Inventor： Chung-Ching Huang ,  Ta-Chuan Liu ,  Tzu-Chiang Chiu ,  Chin-Fa Hsiao

IPC: G06F13/12

CPC classification number: G06F13/385

Abstract: In a method used for initializing a first bus device and a second bus device sharing a common transmission engine of a bus, a first link of the first bus device and a second link of the second bus device to the common transmission engine are disabled when the computer system is booted. Next, the first link and the second link are enabled in order. Then, a first state updating signal from the first bus device is issued after the first link to the common transmission engine is established. Finally, a second state updating signal from the second bus device is issued after the first state updating signal is received and the second link to the common transmission engine is established.

Abstract translation: 在用于初始化共享总线的公共传输引擎的第一总线设备和第二总线设备的方法中，当第一总线设备的第一链路和第二总线设备的第二链路到公共传输引擎时，当第 计算机系统启动。 接下来，按顺序启用第一个链接和第二个链接。 然后，在建立到公共传输引擎的第一链路之后，发出来自第一总线设备的第一状态更新信号。 最后，在接收到第一状态更新信号并建立到公共传输引擎的第二链路之后，发出来自第二总线设备的第二状态更新信号。

公开(公告)号：US20060031690A1

公开(公告)日：2006-02-09

申请号：US10963149

申请日：2004-10-12

Applicant: Chien-Ping Chung ,  Chung-Ching Huang ,  Jing-Rung Wang

Inventor： Chien-Ping Chung ,  Chung-Ching Huang ,  Jing-Rung Wang

IPC: G06F1/30

CPC classification number: G06F1/324 ,  G06F1/3203 ,  Y02D10/126

Abstract: A system and method for power management in computer systems. System status assessed by a Northbridge, and the result transferred to a Southbridge. A system control table is provided in the Southbridge, whereby power management without software control is provided.

Abstract translation: 计算机系统中电源管理的系统和方法。 由北桥评估的系统状态，结果转移到南桥。 在南桥提供了一个系统控制表，从而提供无需软件控制的电源管理。

公开(公告)号：US20080222345A1

公开(公告)日：2008-09-11

申请号：US11945311

申请日：2007-11-27

Applicant: Wen-Juin Huang ,  Chung-Ching Huang ,  Chien-Ping Chung

Inventor： Wen-Juin Huang ,  Chung-Ching Huang ,  Chien-Ping Chung

IPC: G06F12/00

CPC classification number: G06F12/1416 ,  G06F9/30003 ,  G06F2212/2022

Abstract: A memory access method for accessing data from a non-volatile memory in a south bridge is provided. Memory access is performed under a system management mode (SMM). Under the protection of the SMM mode, the desired memory address is not altered by an interrupt handler, therefore memory data is accessed correctly.

Abstract translation: 提供了一种用于从南桥的非易失性存储器访问数据的存储器访问方法。 在系统管理模式（SMM）下执行内存访问。 在SMM模式的保护下，所需的存储器地址不会被中断处理程序改变，因此存储器数据被正确访问。

公开(公告)号：US20080018651A1

公开(公告)日：2008-01-24

申请号：US11522900

申请日：2006-09-19

Applicant: Wen-Juin Huang ,  Chung-Ching Huang ,  Hao-Lin Lin

Inventor： Wen-Juin Huang ,  Chung-Ching Huang ,  Hao-Lin Lin

IPC: G06F15/00

CPC classification number: G06F11/0787 ,  G06F11/0706

Abstract: A method for capturing an image data from a frame buffer of a computer system takes advantage of a system management interrupt service optionally triggered. If a storage unit functions normally when the computer system fails to work normally, store the image data in the frame buffer into the storage unit. Otherwise, temporarily store the image data in a buffer unit, and then store it in a NVRAM. Then restart the storage unit and restore the image data in the buffer unit into the storage unit. At last, restart the computer system.

Abstract translation: 用于从计算机系统的帧缓冲器捕获图像数据的方法利用可选地触发的系统管理中断服务。 如果计算机系统无法正常工作时存储单元正常工作，则将帧缓冲区中的图像数据存储到存储单元中。 否则，将图像数据临时存储在缓冲单元中，然后将其存储在NVRAM中。 然后重新启动存储单元，并将缓冲单元中的图像数据恢复到存储单元中。 最后重新启动计算机系统。

公开(公告)号：US20080010476A1

公开(公告)日：2008-01-10

申请号：US11707966

申请日：2007-02-20

Applicant: Wen-Juin Huang ,  Chung-Ching Huang ,  Jui-Ming Wei

Inventor： Wen-Juin Huang ,  Chung-Ching Huang ,  Jui-Ming Wei

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

Abstract: For saving power of a central processing unit at a C3 power level upon processing a bus master request from a peripheral device, an arbitrator is disabled from transmitting any request to the central processing unit at the C3 power level. Afterwards, in response to a bus master request, the central processing unit is switched from the C3 power level to a transitional C0 power level while keeping the arbitrator disabled, and then switched from the transitional C0 power level to a C2 power level while enabling the arbitrator to process the bus master request.

Abstract translation: 为了在从外围设备处理总线主机请求时以C3功率电平节省中央处理单元的功率，仲裁器被禁止在C3功率电平向中央处理单元发送任何请求。 然后，响应于总线主机请求，中央处理单元从C3功率电平切换到过渡C0功率电平，同时保持仲裁器禁用，然后从过渡C0功率电平切换到C2功率电平，同时使能 仲裁员处理总线主机请求。

公开(公告)号：US20050120154A1

公开(公告)日：2005-06-02

申请号：US11000300

申请日：2004-11-30

Applicant: Tony Ho ,  Chung-Ching Huang ,  Norman Chung

Inventor： Tony Ho ,  Chung-Ching Huang ,  Norman Chung

IPC: G06F13/24

CPC classification number: G06F13/24 ,  Y02D10/14

Abstract: An interruption control system includes an interruption message generator, a stop clock control module and an interruption status indicating path. The interruption message generator is used for decoding and identifying a message signaled interrupt (MSI) issued by a first peripheral device or a second peripheral device when interruption is to be conducted, and generates an interruption status indicating message in response to the message signaled interrupt (MSI). The stop clock control module is coupled to the interruption message generator and the CPU and de-asserts a stop clock signal that is previously asserted to have the CPU enter a power-saving state to have the CPU deactivate the power-saving state in response to the interruption status indicating message. The interruption status indicating path is used for transmitting the interruption status indicating message.

Abstract translation: 中断控制系统包括中断消息发生器，停止时钟控制模块和中断状态指示路径。 所述中断消息发生器用于在进行中断时解码和识别由第一外围设备或第二外围设备发出的消息信号中断（MSI），并响应于消息信号中断产生中断状态指示消息（ MSI）。 停止时钟控制模块耦合到中断消息发生器和CPU，并且取消断言先前断言的停止时钟信号，以使CPU进入省电状态，以使CPU能够响应于CPU 中断状态指示消息。 中断状态指示路径用于发送中断状态指示消息。

公开(公告)号：US20050114723A1

公开(公告)日：2005-05-26

申请号：US10980443

申请日：2004-11-03

Applicant: Tony Ho ,  Chung-Ching Huang ,  Norman Chung

Inventor： Tony Ho ,  Chung-Ching Huang ,  Norman Chung

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3215

Abstract: An interruption control system includes a first input/output interruption controller, a second input/output interruption controller and an interruption status indicating path. The first input/output interruption controller is coupled to a first peripheral device and a south bridge chip, and issues a wake-up signal to the south bridge chip in response to a first interrupt signal asserted by the first peripheral device so as to deactivate a power-saving state of the computer system. The second input/output interruption controller is coupled to a second peripheral device and a north bridge chip, and in response to a second interrupt signal asserted by the second peripheral device, generates a message signaled interrupt. The interruption status indicating path transmits the message signaled interrupt from the second input/output interruption controller to the south bridge chip to have the south bridge chip deactivate the power-saving state of the computer system in response to the message signaled interrupt.

Abstract translation: 中断控制系统包括第一输入/输出中断控制器，第二输入/输出中断控制器和中断状态指示路径。 第一输入/输出中断控制器耦合到第一外围设备和南桥芯片，并且响应于由第一外围设备断言的第一中断信号向南桥芯片发出唤醒信号， 计算机系统的省电状态。 第二输入/输出中断控制器耦合到第二外围设备和北桥芯片，并且响应于由第二外围设备断言的第二中断信号，产生消息信号中断。 中断状态指示路径将消息信号中断从第二输入/输出中断控制器发送到南桥芯片，以使南桥芯片响应于消息信号中断而使计算机系统的省电状态停止。