公开(公告)号：US07162568B2

公开(公告)日：2007-01-09

申请号：US10757464

申请日：2004-01-15

Applicant: Chung-Ching Huang ,  Kuan-Jui Ho

Inventor： Chung-Ching Huang ,  Kuan-Jui Ho

IPC: G06F12/00

CPC classification number: G06F11/2284

Abstract: An apparatus and method of flash ROM management. The apparatus comprises a storage device, a strapping component and a process unit. The storage device stores multiple address records comprising an identity and an address range associated with a flash ROM. The strapping component is configured to output a signal to determine flash ROM type. The process unit receives a memory access request with an access range from the CPU and the signal from the strapping component queries the identity by matching the access range and the address range, and finally executes an LPC 1.1 memory access instruction with the identity and the access range corresponding to the memory cycle.

Abstract translation: 一种闪存ROM管理的设备和方法。 该装置包括存储装置，捆扎部件和处理单元。 存储设备存储包括与快闪ROM相关联的身份和地址范围的多个地址记录。 绑带组件配置为输出信号以确定闪存ROM类型。 处理单元从CPU接收具有访问范围的存储器访问请求，并且来自绑带组件的信号通过匹配访问范围和地址范围来查询身份，并且最终执行具有身份和访问权的LPC 1.1存储器访问指令 范围对应于存储器周期。

公开(公告)号：US08996773B2

公开(公告)日：2015-03-31

申请号：US13485174

申请日：2012-05-31

Applicant: Kuan-Jui Ho ,  Yi-Hsiang Wang ,  Wen-Pin Chiang

Inventor： Kuan-Jui Ho ,  Yi-Hsiang Wang ,  Wen-Pin Chiang

IPC: G06F13/24 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4812 ,  G06F9/5033

Abstract: A computer apparatus and a method for distributing interrupt tasks thereof are provided. The computer apparatus has a plurality of CPUs and a chipset, and the chipset is electrically coupled to each of the CPUs. The chipset is configured for receiving an interrupt request sent from an external hardware device and judging whether or not a task type corresponding to the interrupt request has ever been performed by any one of the CPUs. If a judging result thereof is yes, the chipset assigns the interrupt request to the CPU that has ever performed the task type, so as to perform a corresponding interrupt task.

Abstract translation: 提供了一种用于分发其中断任务的计算机装置和方法。 计算机装置具有多个CPU和芯片组，并且该芯片组电耦合到每个CPU。 芯片组被配置为用于接收从外部硬件设备发送的中断请求，并判断任何一个CPU是否曾执行与中断请求对应的任务类型。 如果其判断结果为是，则芯片组将中断请求分配给已经执行任务类型的CPU，以便执行相应的中断任务。

公开(公告)号：US07549009B2

公开(公告)日：2009-06-16

申请号：US11619047

申请日：2007-01-02

Applicant: Kuan-Jui Ho ,  Wen-Yun Chen

Inventor： Kuan-Jui Ho ,  Wen-Yun Chen

IPC: G06F13/00

CPC classification number: G06F13/4027

Abstract: A high-speed PCI interface system with reset function and a reset method thereof are provided. The interface system comprises a host controller chipset, at least one high-speed PCI device and at least one reset signal generator. While a hot reset packet cannot be executed by the high-speed PCI device, the host controller chipset can respectively transmit a trigger signal and a PCI reset signal to each corresponding reset signal generator through a trigger signal line and a PCI reset signal line, and further the reset signal generator operates to generate a basic resetting signal. Finally, the basic resetting signal will be transmitted to the corresponding high-speed PCI device through a basic reset signal line such that the system can be used to operate the basic resetting action without restarting power.

Abstract translation: 提供具有复位功能的高速PCI接口系统及其复位方法。 接口系统包括主机控制器芯片组，至少一个高速PCI设备和至少一个复位信号发生器。 虽然高速PCI设备不能执行热复位分组，主机控制器芯片组可以通过触发信号线和PCI复位信号线分别将触发信号和PCI复位信号发送到每个相应的复位信号发生器，以及 此外，复位信号发生器操作以产生基本复位信号。 最后，基本的复位信号将通过基本的复位信号线传输到相应的高速PCI设备，使得系统可以用来操作基本的复位动作而不重新启动电源。

公开(公告)号：US07489579B2

公开(公告)日：2009-02-10

申请号：US11425653

申请日：2006-06-21

Applicant: Kuan-Jui Ho

Inventor： Kuan-Jui Ho

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G06F13/1636 ,  G11C11/40626 ,  G11C2211/4061

Abstract: A control device and method are used for adjusting the refresh rate of a memory module in a computer system. The device includes a thermo sensor and a control circuit. In the control method, the thermo sensor actively outputs a temperature change signal in response to the temperature change in the memory module when a capacitor of the memory module incurs an aggravated current leakage due to the temperature rise. Next, the control circuit adjusts the refresh rate in response to the temperature change signal and refreshes the memory module at the refresh rate.

Abstract translation: 控制装置和方法用于调整计算机系统中的存储器模块的刷新率。 该装置包括一个热传感器和一个控制电路。 在控制方法中，当存储器模块的电容器由于温度升高引起加重的电流泄漏时，热敏传感器响应于存储器模块中的温度变化而主动输出温度变化信号。 接下来，控制电路响应于温度变化信号来调整刷新率，并以刷新率刷新存储器模块。

公开(公告)号：US07392372B2

公开(公告)日：2008-06-24

申请号：US11001148

申请日：2004-11-30

Applicant: Hsiu-Ming Chu ,  Kuan-Jui Ho ,  Chung-Che Wu

Inventor： Hsiu-Ming Chu ,  Kuan-Jui Ho ,  Chung-Che Wu

IPC: G06F9/00

CPC classification number: G06F9/4403

Abstract: A memory initialization method for a plurality of memories. The memories are initialized according to predetermined initial parameters. A first quantity of the memories is detected. Optimum parameters are set according hardware information of the memories. The memories are re-initialized according to the optimum parameters. A second quantity of the memories is detected. The parameters for memory initialization are adjusted when the first quantity and the second quantity are different.

Abstract translation: 一种用于多个存储器的存储器初始化方法。 存储器根据预定的初始参数被初始化。 检测第一数量的存储器。 根据存储器的硬件​​信息设置最佳参数。 根据最佳参数重新初始化存储器。 检测到第二数量的存储器。 当第一数量和第二数量不同时，调整存储器初始化的参数。

公开(公告)号：US20070016712A1

公开(公告)日：2007-01-18

申请号：US11414219

申请日：2006-05-01

Applicant: Jen-Chieh Chen ,  Kuan-Jui Ho

Inventor： Jen-Chieh Chen ,  Kuan-Jui Ho

IPC: G06F13/36

CPC classification number: G06F13/404

Abstract: A bridge device electrically connected to a first AGP bus, a second AGP bus, and a PCI bus is provided. The bridge device has a first bridge, a second bridge, and a controller. The first bridge is electrically connected between the first AGP bus and the second AGP bus. The second bridge is electrically connected between the first AGP bus and the PCI bus. The controller is electrically connected to the first AGP bus, the first bridge, and the second bridge. As a configuration cycle corresponding to the first bridge being transmitted through the first AGP bus to the controller, the controller responds a preset message implying that the first bridge does not exist.

Abstract translation: 提供电连接到第一AGP总线，第二AGP总线和PCI总线的桥接器件。 桥接器件具有第一桥，第二桥和控制器。 第一桥电连接在第一AGP总线和第二AGP总线之间。 第二桥电连接在第一AGP总线和PCI总线之间。 控制器电连接到第一AGP总线，第一桥和第二桥。 作为与通过第一AGP总线传送到控制器的第一桥相对应的配置周期，控制器响应预设消息，暗示第一桥不存在。

公开(公告)号：US20060112263A1

公开(公告)日：2006-05-25

申请号：US11126131

申请日：2005-05-10

Applicant: Hsiu-Ming Chu ,  Kuan-Jui Ho

Inventor： Hsiu-Ming Chu ,  Kuan-Jui Ho

IPC: G06F15/177

CPC classification number: G06F13/4027 ,  G06F1/24 ,  Y02D10/14 ,  Y02D10/151

Abstract: A computer reset method activated by a South Bridge to directly reset a Central Processing Unit (CPU). First, a trigger signal is received. A CPU reset signal is delivered by the South Bridge when receiving the trigger signal. Thereafter, the CPU is reset when receiving the CPU reset signal from the South Bridge via a North Bridge.

Abstract translation: 由南桥激活的计算机复位方法直接复位中央处理单元（CPU）。 首先，接收触发信号。 接收到触发信号时，南桥交付CPU复位信号。 此后，通过北桥接收来自南桥的CPU复位信号时，CPU被复位。

公开(公告)号：US07558978B2

公开(公告)日：2009-07-07

申请号：US11377547

申请日：2006-03-17

Applicant: Kuan-Jui Ho

Inventor： Kuan-Jui Ho

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3203

Abstract: A power management device for multiprocessor systems and method thereof applied to force individual processor entering or leaving of a C3 state are disclosed. The device includes at least one checking unit, a plurality of recording units and a plurality of arbiters. The checking unit receives an event from a peripheral device, checks which processor the event corresponds and sends a checking signal. The event is received and recorded by one of the recording units according to the checking signal. Once the recording unit has no record of the received event, the corresponding processor turns the corresponding arbiter off and sends an entering C3 state command. A first control signal is sent to the processor according to the entering C3 state command so as to force the processor into the C3 state.

Abstract translation: 公开了一种用于多处理器系统的电源管理装置及其方法，用于迫使个别处理器进入或离开C3状态。 该装置包括至少一个检查单元，多个记录单元和多个仲裁器。 检查单元从外围设备接收事件，检查事件对应的处理器并发送检查信号。 根据检查信号，一个记录单元接收并记录该事件。 一旦记录单元没有接收到的事件的记录，相应的处理器将相应的仲裁器关闭并发送进入的C3状态命令。 根据进入的C3状态命令将第一控制信号发送到处理器，以迫使处理器进入C3状态。

公开(公告)号：US07506087B2

公开(公告)日：2009-03-17

申请号：US11604812

申请日：2006-11-28

Applicant: Kuan-Jui Ho ,  Min-Hung Chen ,  Hsiou-Ming Chu

Inventor： Kuan-Jui Ho ,  Min-Hung Chen ,  Hsiou-Ming Chu

IPC: G06F13/00

CPC classification number: G06F13/102

Abstract: The present invention relates to a method for configuring a Peripheral Component Interconnect Express (PCIE). A plurality of PCIE parameters are stored in a storage unit. When a computer system starts up, a North Bridge chip is driven to read the PCIE parameters in the storage unit for configuring the PCIE. According to the configuration method of the present invention, when the computer system starts up, the North Bridge chip and the storage unit are enabled first. Then, the North Bridge chip is driven to read the PCIE parameters. Finally, the North Bridge chip proceeds with initialization according to the PCIE parameters to configure PCIE.

Abstract translation: 本发明涉及一种用于配置外围组件互连Express（PCIE）的方法。 多个PCIE参数被存储在存储单元中。 当计算机系统启动时，驱动北桥芯片读取存储单元中的PCIE参数以配置PCIE。 根据本发明的配置方法，当计算机系统启动时，首先启用北桥芯片和存储单元。 然后，驱动北桥芯片读取PCIE参数。 最后，北桥芯片根据PCIE参数进行初始化，配置PCIE。

公开(公告)号：US20070124610A1

公开(公告)日：2007-05-31

申请号：US11377547

申请日：2006-03-17

Applicant: Kuan-Jui Ho

Inventor： Kuan-Jui Ho

IPC: G06F1/00

CPC classification number: G06F1/3203

Abstract: A power management device for multiprocessor systems and method thereof applied to force individual processor entering or leaving of a C3 state are disclosed. The device includes at least one checking unit, a plurality of recording units and a plurality of arbiters. The checking unit receives an event from a peripheral device, checks which processor the event corresponds and sends a checking signal. The event is received and recorded by one of the recording units according to the checking signal. Once the recording unit has no record of the received event, the corresponding processor turns the corresponding arbiter off and sends an entering C3 state command. A first control signal is sent to the processor according to the entering C3 state command so as to force the processor into the C3 state.

Abstract translation: 公开了一种用于多处理器系统的电源管理装置及其方法，用于迫使个别处理器进入或离开C3状态。 该装置包括至少一个检查单元，多个记录单元和多个仲裁器。 检查单元从外围设备接收事件，检查事件对应的处理器并发送检查信号。 根据检查信号，一个记录单元接收并记录该事件。 一旦记录单元没有接收到的事件的记录，相应的处理器将相应的仲裁器关闭并发送进入的C3状态命令。 根据进入的C3状态命令将第一控制信号发送到处理器，以迫使处理器进入C3状态。