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    Non-volatile memory and method of fabricating the same
    1.
    发明授权
    Non-volatile memory and method of fabricating the same 有权
    非易失性存储器及其制造方法

    公开(公告)号：US07342280B2

    公开(公告)日：2008-03-11

    申请号：US11149396

    申请日：2005-06-09

    申请人： Tae-kwang Yoo

    发明人： Tae-kwang Yoo

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/42352 ,  H01L29/66833

    摘要： An electrically erasable programmable read-only memory (EEPROM) comprises trench isolation regions whose upper surfaces are recessed compared with an upper surface of the semiconductor substrate, thereby allowing use of all surfaces of a protrusion of the semiconductor substrate between the isolation regions, including the upper surface of the semiconductor substrate, as an active region. Accordingly, the performance of a memory cell can be improved by increasing the size of an active channel region without needing to change the size of a planar unit cell.

    摘要翻译： 电可擦除可编程只读存储器（EEPROM）包括与半导体衬底的上表面相比上表面凹陷的沟槽隔离区域，从而允许在隔离区域之间使用半导体衬底的突起的所有表面，包括 半导体衬底的上表面作为有源区。 因此，可以通过增加有源沟道区的尺寸而不需要改变平面单元的尺寸来提高存储单元的性能。

    Nonvolatile memory devices
    4.
    发明授权
    Nonvolatile memory devices 有权
    非易失性存储器件

    公开(公告)号：US07183157B2

    公开(公告)日：2007-02-27

    申请号：US10867152

    申请日：2004-06-14

    申请人： Tae-Kwang Yoo ,  Jeong-Uk Han

    发明人： Tae-Kwang Yoo ,  Jeong-Uk Han

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324

    摘要： Nonvolatile memory devices and methods for fabricating the same are provided. The device includes first and second base patterns disposed under floating and selection gates, respectively, at an active region. A channel region is formed in the active region between the first and second base patterns, and source and drain regions are formed in the active region adjacent to the first and second base patterns, respectively. The method includes forming first and second base patterns on a semiconductor substrate to be separated from each other by a predetermined space. A channel region is formed in the semiconductor substrate between the first and second base patterns. Source and drain regions are formed in the semiconductor substrate adjacent to the reverse side of the channel region on the basis of the first and second base patterns, respectively. A tunnel oxide layer is formed on a predetermined region of the channel region. A memory gate is formed to cover the first base pattern and the tunnel oxide layer. A selection gate pattern is then formed to cover the second base pattern.

    摘要翻译： 提供非易失性存储器件及其制造方法。 该装置包括分别设置在有源区域的浮动选择栅极下的第一和第二基本图案。 在第一和第二基底图案之间的有源区中形成沟道区，并且分别在与第一和第二基底图案相邻的有源区中形成源极和漏极区。 该方法包括在半导体衬底上形成第一和第二基底图案以彼此分开预定的空间。 在第一和第二基底图案之间的半导体衬底中形成沟道区。 源区和漏区分别基于第一和第二基底图案形成在与沟道区的相反侧相邻的半导体衬底中。 隧道氧化层形成在沟道区的预定区域上。 形成存储栅极以覆盖第一基底图案和隧道氧化物层。 然后形成选择栅极图案以覆盖第二基底图案。

    Engine control with operating mode detection
    5.
    发明授权
    Engine control with operating mode detection 有权
    发动机控制与操作模式检测

    公开(公告)号：US06860244B2

    公开(公告)日：2005-03-01

    申请号：US10065681

    申请日：2002-11-08

    申请人： Christopher Paul Glugla ,  David Karl Trumpy ,  In Kwang Yoo ,  William Robert Dutcher ,  Woong-chul Yang

    发明人： Christopher Paul Glugla ,  David Karl Trumpy ,  In Kwang Yoo ,  William Robert Dutcher ,  Woong-chul Yang

    IPC分类号： F02D15/02 ,  F02D41/14 ,  F02D41/22 ,  F02P5/15 ,  F02P5/152 ,  F02B33/04

    CPC分类号： F02D35/027 ,  F02D15/02 ,  F02D41/1408 ,  F02D41/22 ,  F02P5/1504 ,  F02P5/1521 ,  Y02T10/46

    摘要： A system and method for detecting an operating mode of an engine or engine component modulate a first engine parameter and analyze a change in a second engine parameter in response to modulating the first engine parameter to detect a current operating mode based on changes in at least one of the first and second engine parameters. In a variable compression ratio (VCR) engine embodiment, the system and method modify ignition timing of at least one cylinder until engine knock is detected and determine whether the cylinder is operating in the lower compression ratio mode or the higher compression ratio mode by comparing the ignition timing change required to cause engine knock to a corresponding threshold.

    摘要翻译： 用于检测发动机或发动机部件的操作模式的系统和方法调节第一发动机参数并且响应于调制第一发动机参数来分析第二发动机参数的变化，以基于至少一个发动机参数的变化来检测当前运行模式 的第一和第二引擎参数。 在可变压缩比（VCR）发动机实施例中，系统和方法修改了至少一个气缸的点火正时，直到检测到发动机爆震，并且通过比较该压缩比模式或较高压缩比模式来确定气缸是否工作 发动机撞击所需的点火正时变化达到相应的阈值。

    MEMORY SYSTEM WITH MULTIPLE CHANNEL INTERFACES AND METHOD OF OPERATING SAME
    7.
    发明申请
    MEMORY SYSTEM WITH MULTIPLE CHANNEL INTERFACES AND METHOD OF OPERATING SAME 审中-公开
    具有多个通道接口的记忆系统及其操作方法

    公开(公告)号：US20160299525A1

    公开(公告)日：2016-10-13

    申请号：US14995834

    申请日：2016-01-14

    申请人： YOUNG-JIN CHO ,  JAE-GEUN PARK ,  YOUNG-KWANG YOO ,  SOON-SUK HWANG

    发明人： YOUNG-JIN CHO ,  JAE-GEUN PARK ,  YOUNG-KWANG YOO ,  SOON-SUK HWANG

    IPC分类号： G06F1/10

    CPC分类号： G06F1/10 ,  G06F1/04 ,  G06F5/06

    摘要： A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

    摘要翻译： 一种存储器系统，包括具有通道通道的存储器组的存储器控​​制器。 每个通道接口将控制，地址和/或数据（CAD）信号与从输入时钟导出的从时钟同步地传送到与频道连接的存储器组。 通过应用信道接口专用相位/频率调制或时间延迟来唯一地产生各种从时钟，使得各个CAD信号的特征在于倾斜的转换时序。

    Non-volatile memory device and method of fabricating the same
    10.
    发明授权
    Non-volatile memory device and method of fabricating the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US07344949B2

    公开(公告)日：2008-03-18

    申请号：US11444186

    申请日：2006-05-31

    申请人： Tae-kwang Yoo

    发明人： Tae-kwang Yoo

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/42352 ,  H01L29/66833

    摘要： A method of fabricating an a non-volatile memory includes forming trench isolation regions in an inactive region of a semiconductor substrate, adjacent trench isolation regions defining respective protrusions having rounded edges therebetween, wherein upper surfaces of the trench isolation regions are lower than an upper surface of the semiconductor substrate and wherein the protrusions define an active region, forming a tunnel insulating layer covering the protrusion of the semiconductor substrate, and forming, sequentially, a storage layer, a blocking insulating layer, and a gate layer covering the tunnel insulating layer.

    摘要翻译： 一种制造非易失性存储器的方法包括在半导体衬底的非活性区域中形成沟槽隔离区域，邻近沟槽隔离区域限定在其间具有圆形边缘的相应突起，其中沟槽隔离区域的上表面比上表面 并且其中所述突起限定有源区，形成覆盖所述半导体衬底的所述突起的隧道绝缘层，以及依次形成覆盖所述隧道绝缘层的存储层，阻挡绝缘层和栅极层。