公开(公告)号：US07816137B2

公开(公告)日：2010-10-19

申请号：US10587398

申请日：2005-01-31

申请人： Myoung Woo Lee ,  Young Jin Kim ,  Jeong Eun Choi ,  Mal Sook Yang ,  Young Joon Moon ,  Sun Kyung Kim ,  Hugh Chul Kim ,  Joon Seong Park ,  In Keun Jang

发明人： Myoung Woo Lee ,  Young Jin Kim ,  Jeong Eun Choi ,  Mal Sook Yang ,  Young Joon Moon ,  Sun Kyung Kim ,  Hugh Chul Kim ,  Joon Seong Park ,  In Keun Jang

IPC分类号： C12N5/00

CPC分类号： C12N5/0658 ,  C12N5/0619 ,  C12N5/0647 ,  C12N5/0654 ,  C12N5/067 ,  C12N2501/12 ,  C12N2501/13 ,  C12N2501/165 ,  C12N2501/22 ,  C12N2501/23 ,  C12N2501/25 ,  C12N2506/11

摘要： Since the multipotent progenitor/stem cells isolated and cultured from the cord blood-derived mononuclear cells according to the method of the present invention are capable of differentiating into several types of cells including neurons, osteoblasts, myoblasts, endothelial cells, hepatocytes and dendritic cells, they can be effectively used for a cell therapy, a cell restoration technique or an organ production.

摘要翻译： 由于根据本发明的方法从脐带血衍生的单核细胞分离和培养的多能祖细胞/干细胞能够分化成包括神经元，成骨细胞，成肌细胞，内皮细胞，肝细胞和树突状细胞在内的几种细胞， 它们可以有效地用于细胞治疗，细胞恢复技术或器官生产。

公开(公告)号：US20100065919A1

公开(公告)日：2010-03-18

申请号：US12621079

申请日：2009-11-18

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L27/092

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

公开(公告)号：US20060003574A1

公开(公告)日：2006-01-05

申请号：US11099534

申请日：2005-04-06

申请人： Jae-Hak Kim ,  Kyoung-Woo Lee ,  Hong-Jae Shin ,  Young-Joon Moon ,  Seo-Woo Nam

发明人： Jae-Hak Kim ,  Kyoung-Woo Lee ,  Hong-Jae Shin ,  Young-Joon Moon ,  Seo-Woo Nam

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808

摘要： A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling the preliminary via hole in a subsequent trench formation process. The sacrificial layer and the layer filling the preliminary via hole are simultaneously removed after the trench formation process is carried out. According to another embodiment, a thin capping oxide layer is formed on an insulating interlayer during the formation of a preliminary via hole. The thin capping oxide layer is removed together with a sacrificial layer after a trench formation process is carried out.

摘要翻译： 公开了一种使用双镶嵌工艺形成通孔接触结构的方法。 根据一个实施例，在形成预通孔期间，在绝缘中间层上形成牺牲层。 牺牲层具有与随后的沟槽形成过程中填充预通孔的层相同的组成。 在进行沟槽形成处理之后，同时去除牺牲层和填充预通孔的层。 根据另一实施例，在形成预通孔期间，在绝缘中间层上形成薄封盖氧化物层。 在进行沟槽形成处理之后，薄层氧化物层与牺牲层一起被去除。

公开(公告)号：US07759185B2

公开(公告)日：2010-07-20

申请号：US11853187

申请日：2007-09-11

申请人： Seo-woo Nam ,  Young-joon Moon ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Young-joon Moon ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/823871 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first stress film covering a first gate electrode and first source/drain areas of a first transistor area and at least a portion of a third gate electrode of an interface area, a second stress film covering a second gate electrode and second source/drain areas of a second transistor area and overlapping at least a portion of the first stress film on the third gate electrode of the interface area, and an interlayer insulating film formed on the first and the second stress film. The semiconductor device further includes a plurality of first contact holes formed through the interlayer insulating film and the first stress film in the first transistor area to expose the first gate electrode and the first source/drain areas, a plurality of second contact holes formed through the interlayer insulating film and the second stress film in the second transistor area to expose the second gate electrode and the second source/drain areas, and a third contact hole formed through the interlayer insulating film, the second stress film, and the first stress film in the interface area to expose the third gate electrode. A depth of a recessed portion of an upper side of the third gate electrode in which the third contact hole is formed is equal to or larger than a depth of a recessed portion of an upper side of the first gate electrode in which the first contact hole is formed.

摘要翻译： 半导体器件包括覆盖第一栅电极的第一应力膜和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅电极的至少一部分，覆盖第二栅电极的第二应力膜和第二应力膜 第二晶体管区域的源极/漏极区域，并且与界面区域的第三栅电极上的第一应力膜的至少一部分重叠，以及形成在第一和第二应力膜上的层间绝缘膜。 半导体器件还包括多个通过层间绝缘膜形成的第一接触孔和第一晶体管区域中的第一应力膜，以暴露第一栅极电极和第一源极/漏极区域，形成多个第二接触孔 层间绝缘膜和第二晶体管区域中的第二应力膜，以暴露第二栅电极和第二源极/漏极区，以及通过层间绝缘膜，第二应力膜和第一应力膜形成的第三接触孔 暴露第三栅电极的界面区域。 形成第三接触孔的第三栅电极的上侧的凹部的深度等于或大于第一栅电极的上侧的凹部的深度，其中第一接触孔 形成了。

公开(公告)号：US07638423B2

公开(公告)日：2009-12-29

申请号：US11701420

申请日：2007-02-02

申请人： Jung-eun Lee ,  Young-jin Wee ,  Andrew-tae Kim ,  Young-joon Moon

发明人： Jung-eun Lee ,  Young-jin Wee ,  Andrew-tae Kim ,  Young-joon Moon

IPC分类号： H01L21/4763

CPC分类号： H01L23/53295 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76844 ,  H01L21/76864 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming wires of a semiconductor device including forming a first metal wire on a semiconductor substrate; forming a first insulating film on the first metal wire; etching a portion of the first insulating film to expose a surface portion of the first metal wire; forming a first barrier metal film on sidewalls of the opening and the exposed first metal wire; etching a portion of the first barrier metal film on the first metal wire to expose a surface portion of the first metal wire; performing a heat treatment process on the exposed surface portion of the first metal wire to improve surface roughness; and forming a second wire by filling the opening using a conductive material.

摘要翻译： 一种形成半导体器件的线的方法，包括在半导体衬底上形成第一金属线; 在所述第一金属线上形成第一绝缘膜; 蚀刻第一绝缘膜的一部分以暴露第一金属线的表面部分; 在开口的侧壁和暴露的第一金属线上形成第一阻挡金属膜; 蚀刻第一金属线上的第一阻挡金属膜的一部分以暴露第一金属线的表面部分; 对所述第一金属线的暴露表面部进行热处理，以改善表面粗糙度; 以及通过使用导电材料填充所述开口而形成第二线。

公开(公告)号：US20080079087A1

公开(公告)日：2008-04-03

申请号：US11851500

申请日：2007-09-07

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

公开(公告)号：US07064059B2

公开(公告)日：2006-06-20

申请号：US10939930

申请日：2004-09-13

申请人： Jae-Hak Kim ,  Young-Joon Moon ,  Kyoung-Woo Lee ,  Jeong-Wook Hwang

发明人： Jae-Hak Kim ,  Young-Joon Moon ,  Kyoung-Woo Lee ,  Jeong-Wook Hwang

IPC分类号： H01L21/4763 ,  H01L21/311 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76808 ,  H01L21/31144

摘要： There is provided a method of forming a dual damascene metal interconnection by employing a sacrificial metal oxide layer. The method includes preparing a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate, and a preliminary via hole is formed by patterning the interlayer insulating layer. A sacrificial via protecting layer is formed on the semiconductor substrate having the preliminary via hole to fill the preliminary via hole, and cover an upper surface of the interlayer insulating layer. A sacrificial metal oxide layer is formed on the sacrificial via protecting layer, the sacrificial metal oxide layer is patterned to form a sacrificial metal oxide pattern having an opening crossing over the preliminary via hole, and exposing the sacrificial via protecting layer. The sacrificial via protecting layer and the interlayer insulating layer are etched using the sacrificial metal oxide pattern as an etch mask to form a trench located inside the interlayer insulating layer.

摘要翻译： 提供了通过使用牺牲金属氧化物层形成双镶嵌金属互连的方法。 该方法包括制备半导体衬底。 在半导体基板上形成层间绝缘层，通过图案化层间绝缘层形成预备通孔。 在具有初步通孔的半导体衬底上形成牺牲通孔保护层以填充预通孔，并覆盖层间绝缘层的上表面。 在牺牲通路保护层上形成牺牲金属氧化物层，对牺牲金属氧化物层进行图案化以形成具有穿过预通孔的开口的牺牲金属氧化物图案，并且将牺牲通过保护层曝光。 使用牺牲金属氧化物图案作为蚀刻掩模蚀刻牺牲通过保护层和层间绝缘层，以形成位于层间绝缘层内部的沟槽。

公开(公告)号：US07902609B2

公开(公告)日：2011-03-08

申请号：US12621079

申请日：2009-11-18

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L23/62

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

公开(公告)号：US20060183280A1

公开(公告)日：2006-08-17

申请号：US11352660

申请日：2006-02-13

申请人： Sang-Jin Lee ,  Young-Joon Moon ,  Seung-Koo Lee ,  Kyung-Tae Lee

发明人： Sang-Jin Lee ,  Young-Joon Moon ,  Seung-Koo Lee ,  Kyung-Tae Lee

IPC分类号： H01L21/8242

CPC分类号： H01L21/76816 ,  H01L21/76807 ,  H01L28/60

摘要： There are provided metal-insulator-metal (MIM) capacitors and methods of forming the same. The capacitors and the formation methods thereof provide a way of simplifying semiconductor fabrication processes, using component elements of the capacitor and insulating layers around the capacitor. To this end, lower and upper electrodes are sequentially stacked on a semiconductor substrate. A dielectric layer pattern is interposed between the upper and lower electrodes. An etch stop layer pattern and an etch buffer layer are disposed on the upper electrode and under the lower electrode, respectively. The upper and lower electrodes are disposed to expose the dielectric layer pattern and the etch buffer layer.

摘要翻译： 提供金属 - 绝缘体 - 金属（MIM）电容器及其形成方法。 电容器及其形成方法提供了使用电容器的元件和电容器周围的绝缘层来简化半导体制造工艺的方法。 为此，下电极和上电极依次堆叠在半导体衬底上。 电介质层图案插入在上电极和下电极之间。 蚀刻停止层图案和蚀刻缓冲层分别设置在上电极和下电极下。 上电极和下电极被设置为暴露电介质层图案和蚀刻缓冲层。

公开(公告)号：US20050124149A1

公开(公告)日：2005-06-09

申请号：US10939930

申请日：2004-09-13

申请人： Jae-Hak Kim ,  Young-Joon Moon ,  Kyoung-Woo Lee ,  Jeong-Wook Hwang

发明人： Jae-Hak Kim ,  Young-Joon Moon ,  Kyoung-Woo Lee ,  Jeong-Wook Hwang

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76808 ,  H01L21/31144

摘要： There is provided a method of forming a dual damascene metal interconnection by employing a sacrificial metal oxide layer. The method includes preparing a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate, and a preliminary via hole is formed by patterning the interlayer insulating layer. A sacrificial via protecting layer is formed on the semiconductor substrate having the preliminary via hole to fill the preliminary via hole, and cover an upper surface of the interlayer insulating layer. A sacrificial metal oxide layer is formed on the sacrificial via protecting layer, the sacrificial metal oxide layer is patterned to form a sacrificial metal oxide pattern having an opening crossing over the preliminary via hole, and exposing the sacrificial via protecting layer. The sacrificial via protecting layer and the interlayer insulating layer are etched using the sacrificial metal oxide pattern as an etch mask to form a trench located inside the interlayer insulating layer.

摘要翻译： 提供了通过使用牺牲金属氧化物层形成双镶嵌金属互连的方法。 该方法包括制备半导体衬底。 在半导体基板上形成层间绝缘层，通过图案化层间绝缘层形成预备通孔。 在具有初步通孔的半导体衬底上形成牺牲通孔保护层以填充预通孔，并覆盖层间绝缘层的上表面。 在牺牲通路保护层上形成牺牲金属氧化物层，对牺牲金属氧化物层进行图案化以形成具有穿过预通孔的开口的牺牲金属氧化物图案，并且将牺牲通过保护层曝光。 使用牺牲金属氧化物图案作为蚀刻掩模蚀刻牺牲通过保护层和层间绝缘层，以形成位于层间绝缘层内部的沟槽。