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公开(公告)号：US09069555B2
公开(公告)日：2015-06-30
申请号：US13422476
申请日：2012-03-16
申请人： Eric Fetzer , Reid J. Reidlinger , Don Soltis , William J. Bowhill , Satish Shrimali , Krishnakanth Sistla , Efraim Rotem , Rakesh Kumar , Vivek Garg , Alon Naveh , Lokesh Sharma
发明人： Eric Fetzer , Reid J. Reidlinger , Don Soltis , William J. Bowhill , Satish Shrimali , Krishnakanth Sistla , Efraim Rotem , Rakesh Kumar , Vivek Garg , Alon Naveh , Lokesh Sharma
CPC分类号： G06F1/3296 , G06F1/324 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the dynamic capacitance of the processor such that the dynamic capacitance is within an allowable dynamic capacitance value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.
摘要翻译： 处理器可以包括核心和无孔区域。 可以通过控制处理器的动态电容来控制核心区域消耗的功率，使得动态电容在允许的动态电容值内，而不管应用程序是否被核心区域处理。 电源管理技术包括测量数字活动因素（DAF），监控架构和数据活动级别，以及通过基于活动级别来限制指令来控制功耗。 作为节流指令的结果，节流可以在第3垂直和热设计点（TDP）中实现。 此外，通过改变提供给无孔区域的参考电压VR和VP，可以减少核心区域处于深功率节省状态时由无孔区域消耗的空闲功率。 结果，可以减少由无孔区域消耗的空闲功率。
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公开(公告)号：US20160147280A1
公开(公告)日：2016-05-26
申请号：US14554585
申请日：2014-11-26
申请人： Tessil Thomas , Lokesh Sharma , Buck W. Gremel , Ian M. Steiner
发明人： Tessil Thomas , Lokesh Sharma , Buck W. Gremel , Ian M. Steiner
CPC分类号： G06F1/206 , G06F1/3243 , Y02D10/152 , Y02D10/16
摘要： In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括执行指令的至少一个核心，与所述至少一个核心相关联的一个或多个热传感器以及耦合到所述至少一个核心的功率控制器。 功率控制器具有用于接收关于处理器的温度信息的控制逻辑，并且至少部分地基于温度信息动态地确定最大允许平均功率限制。 控制逻辑可以进一步保持处理器的静态最大基本操作频率，而不管温度信息的值。 描述和要求保护其他实施例。
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公开(公告)号：US20130232368A1
公开(公告)日：2013-09-05
申请号：US13782492
申请日：2013-03-01
申请人： ERIC FETZER , REID RIEDLINGER , DON SOLTIS , WILLIAM BOWHILL , SATISH SHRIMALI , KRISHNAKANTH SISTLA , EFRAIM ROTEM , RAKESH KUMAR , VIVEK GARG , ALON NAVEH , LOKESH SHARMA
发明人： ERIC FETZER , REID RIEDLINGER , DON SOLTIS , WILLIAM BOWHILL , SATISH SHRIMALI , KRISHNAKANTH SISTLA , EFRAIM ROTEM , RAKESH KUMAR , VIVEK GARG , ALON NAVEH , LOKESH SHARMA
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/324 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.
摘要翻译： 处理器可以包括核心和无孔区域。 可以通过控制处理器的Cdyn来控制核心区域消耗的功率，使得Cdyn处于可允许的Cdyn值内，而不管应用程序是否被核心区域处理。 电源管理技术包括测量数字活动因素（DAF），监控架构和数据活动级别，以及通过基于活动级别来限制指令来控制功耗。 作为节流指令的结果，节流可以在第3垂直和热设计点（TDP）中实现。 此外，通过改变提供给无孔区域的参考电压VR和VP，可以减少核心区域处于深功率节省状态时由无孔区域消耗的空闲功率。 结果，可以减少由无孔区域消耗的空闲功率。
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公开(公告)号：US20120254643A1
公开(公告)日：2012-10-04
申请号：US13422476
申请日：2012-03-16
申请人： Eric Fetzer , Reid J. Reidlinger , Don Soltis , William J. Bowhill , Satish Shrimali , Krishnakanth Sistla , Efraim Rotem , Rakesh Kumar , Vivek Garg , Alon Naveh , Lokesh Sharma
发明人： Eric Fetzer , Reid J. Reidlinger , Don Soltis , William J. Bowhill , Satish Shrimali , Krishnakanth Sistla , Efraim Rotem , Rakesh Kumar , Vivek Garg , Alon Naveh , Lokesh Sharma
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/324 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.
摘要翻译： 处理器可以包括核心和无孔区域。 可以通过控制处理器的Cdyn来控制核心区域消耗的功率，使得Cdyn处于可允许的Cdyn值内，而不管应用程序是否被核心区域处理。 电源管理技术包括测量数字活动因素（DAF），监控架构和数据活动级别，以及通过基于活动级别来限制指令来控制功耗。 作为节流指令的结果，节流可以在第3垂直和热设计点（TDP）中实现。 此外，通过改变提供给无孔区域的参考电压VR和VP，可以减少核心区域处于深功率节省状态时由无孔区域消耗的空闲功率。 结果，可以减少由无孔区域消耗的空闲功率。
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