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1.发明授权Very long instruction word microprocessor with execution packet spanning two or more fetch packets with pre-dispatch instruction selection from two latches according to instruction bit 有权非常长的指令字微处理器，执行数据包跨越两个或更多个取指数据包，根据指令位从两个锁存器中进行预调度指令选择公开(公告)号：US07039790B1
公开(公告)日：2006-05-02
申请号：US09702320
申请日：2000-10-31
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3816 , G06F9/3824 , G06F9/3828 , G06F9/3885
摘要： A data processing system with a microprocessor. The microprocessor has an instruction execution pipeline including fetch and decode stages and several functional execution units. Fetch packets contain a plurality of instruction words. Execute packets include a plurality of instruction words that can be executed in parallel by two or more execution units. An execution packet can span two or more fetch packets. A predetermined bit in each instruction marks whether the next instruction is executed in parallel with the current instruction. Instructions in an execute packet are dispatched to appropriate functional execution units based on instruction type. Upon a branch into an execute packet instructions at memory addresses before the branch location are not executed in parallel with instructions following the branch location.
摘要翻译： 具有微处理器的数据处理系统。 微处理器具有指令执行流水线，其中包括读取和解码级以及若干功能执行单元。 获取分组包含多个指令字。 执行分组包括可由两个或多个执行单元并行执行的多个指令字。 执行分组可以跨越两个或更多个获取分组。 每个指令中的预定位标记下一条指令是否与当前指令并行执行。 执行数据包中的指令根据指令类型调度到适当的功能执行单元。 在分支位置不与执行分支位置之后的指令并行执行之前，在分支进入存储器地址的执行分组指令。
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公开(公告)号：US5841379A
公开(公告)日：1998-11-24
申请号：US788751
申请日：1997-01-24
IPC分类号： H03M7/46
CPC分类号： H03M7/46
摘要： A method for compression of digital data in a computer having a processor and a memory, wherein a group of consecutive bits having the same binary value is represented by a result number corresponding to the number of the consecutive bits. The method involves the following steps. A block of digital data to be compressed is provided. A bit detect selection parameter determines a bit value to be counted for counting consecutive bits. The processor is instructed to count from a first end of the block of digital data toward a second end of the block of digital data the number of consecutive bits having the bit value determined by the bit detect selection parameter. The number of bits so counted is stored, and the bit detect selection parameter is toggled. The processor is then instructed to count from the last bit counted toward the second end of the block of digital data the number of bits having the bit value determined by the current bit detect selection parameter. The foregoing steps are repeated, with successive numbers being stored representing the number of bits counted in successive counts as successive stored result numbers, until all bits in the block of digital data are counted.
摘要翻译： 一种用于在具有处理器和存储器的计算机中压缩数字数据的方法，其中具有相同二进制值的一组连续位由对应于连续位数的结果编号表示。 该方法包括以下步骤。 提供要压缩的数字数据块。 位检测选择参数确定要计数连续位的位值。 指示处理器从数字数据块的第一端向数字数据块的第二端计数具有由位检测选择参数确定的位值的连续位的数目。 存储如此计数的位数，并且切换位检测选择参数。 然后指示处理器从由数字数据块的第二端计数的最后位计数具有由当前位检测选择参数确定的位值的位数。 重复上述步骤，连续的数字被存储，表示以连续计数计数的位数作为连续存储的结果编号，直到对数字数据块中的所有位进行计数。
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3.发明授权Processing devices with improved addressing capabilities, systems and methods 失效具有改进的寻址能力，系统和方法的处理设备
公开(公告)号：US5305446A
公开(公告)日：1994-04-19
申请号：US589968
申请日：1990-09-28
CPC分类号： G06F9/327 , G06F9/3016 , G06F9/30167 , G06F9/32 , G06F9/321 , G06F9/324 , G06F9/325 , G06F9/342 , G06F9/345 , G06F9/355 , G06F9/3822 , G06F9/3842 , G06F9/3861 , G06F9/3879 , G06F9/3885
摘要： A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data. Further included is an address generating unit connected to the storage circuit, the instruction register, and the address register responsive to the control signals from the instruction decode and control unit combining the initial address word from the address register and the address data from the displacement section to generate a storage circuit address. Other devices, systems and methods are also disclosed.
摘要翻译： 一种数据处理装置，包括通过断言地址可访问的存储电路，连接到存储电路的算术逻辑单元，用于对由算术单元接收的数据执行算术运算。 还包括用于存储表示存储电路地址的初始地址字的地址寄存器。 连接到存储电路并且具有用于保存程序指令的指令寄存器的指令解码和控制单元用于将程序指令解码为控制信号，以控制数据处理设备的操作和位置代码以根据 到所述程序指令的预定部分，其中所述部分中的至少一个包括选择所述地址寄存器的位置部分和包含地址数据的位移部分。 还包括地址生成单元，其响应于来自地址寄存器的初始地址字的指令解码和控制单元的控制信号和来自位移部分的地址数据而连接到存储电路，指令寄存器和地址寄存器 以产生存储电路地址。 还公开了其他装置，系统和方法。
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公开(公告)号：US5594914A
公开(公告)日：1997-01-14
申请号：US326677
申请日：1994-10-20
CPC分类号： G06F9/30043 , G06F9/34 , G06F9/3842 , G06F9/3861
摘要： A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an instruction decode and control unit, having an instruction register operative to hold a program instruction, operative to decode a program instruction providing control signals according to a pipeline organization to control the operations of the data processing device within each instruction cycle and to initiate a block sequence responsive to an instruction code representing a block instruction. A program sequencer circuit, having a program register to hold a program count corresponding to a program address, is operative to access the memory with the contents of the program register to obtain the program instruction corresponding to the program address. Further included is an arithmetic logic unit operative to perform an arithmetic operation on data received by the arithmetic unit and to combine the contents of the program register with a data field decoded from the block instruction by the instruction decode and control unit to generate a block end address, and a block handler unit, having a block start register operative to store the contents of the program register, is responsive to the control signals from the instruction decode and control unit to store the program address corresponding to the block start address to the block start register wherein the contents of the block start register correspond to a start address for a block of instructions to be executed. Other devices, systems and methods are also disclosed.
摘要翻译： 一种数据处理装置，包括用于产生建立指令周期的脉冲的时钟发生器，通过断言地址可访问的存储器，指令解码和控制单元，具有可操作以保存程序指令的指令寄存器，用于解码提供控制信号的程序指令 根据管理组织来控制每个指令周期内的数据处理设备的操作，并且响应于表示块指令的指令代码启动块序列。 具有用于保存与程序地址相对应的程序计数的程序寄存器的程序定序器电路可操作以利用程序寄存器的内容访问存储器，以获得与程序地址相对应的程序指令。 进一步包括的算术逻辑单元可操作以对由算术单元接收的数据进行算术运算，并将程序寄存器的内容与由指令解码和控制单元从块指令解码的数据字段组合，以生成块结束 地址和块处理器单元，具有用于存储程序寄存器的内容的块起始寄存器，响应于来自指令解码和控制单元的控制信号，将对应于块起始地址的程序地址存储到块 起始寄存器，其中块起始寄存器的内容对应于要执行的指令块的起始地址。 还公开了其他装置，系统和方法。
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公开(公告)号：US5535348A
公开(公告)日：1996-07-09
申请号：US420932
申请日：1995-04-12
CPC分类号： G06F9/30043 , G06F9/34 , G06F9/3842 , G06F9/3861
摘要： A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an instruction decode and control unit, having an instruction register operative to hold a program instruction, operative to decode a program instruction providing control signals according to a pipeline organization to control the operations of the data processing device within each instruction cycle and to initiate a block sequence responsive to an instruction code representing a block instruction. A program sequencer circuit, having a program register to hold a program count corresponding to a program address, is operative to access the memory with the contents of the program register to obtain the program instruction corresponding to the program address. Further included is an arithmetic logic unit operative to perform an arithmetic operation on data received by the arithmetic unit and to combine the contents of the program register with a data field decoded from the block instruction by the instruction decode and control unit to generate a block end address, and a block handler unit, having a block start register operative to store the contents of the program register, is responsive to the control signals from the instruction decode and control unit to store the program address corresponding to the block start address to the block start register wherein the contents of the block start register correspond to a start address for a block of instructions to be executed. Other devices, systems and methods are also disclosed.
摘要翻译： 一种数据处理装置，包括用于产生建立指令周期的脉冲的时钟发生器，通过断言地址可访问的存储器，指令解码和控制单元，具有可操作以保存程序指令的指令寄存器，用于解码提供控制信号的程序指令 根据管理组织来控制每个指令周期内的数据处理设备的操作，并且响应于表示块指令的指令代码启动块序列。 具有用于保存与程序地址相对应的程序计数的程序寄存器的程序定序器电路可操作以利用程序寄存器的内容访问存储器，以获得与程序地址相对应的程序指令。 进一步包括的算术逻辑单元可操作以对由算术单元接收的数据进行算术运算，并将程序寄存器的内容与由指令解码和控制单元从块指令解码的数据字段组合，以生成块结束 地址和块处理器单元，具有用于存储程序寄存器的内容的块起始寄存器，响应于来自指令解码和控制单元的控制信号，将对应于块起始地址的程序地址存储到块 起始寄存器，其中块起始寄存器的内容对应于要执行的指令块的起始地址。 还公开了其他装置，系统和方法。
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公开(公告)号：US5511146A
公开(公告)日：1996-04-23
申请号：US259373
申请日：1994-06-14
CPC分类号： G06N3/004
摘要： A set of three cellular automata--the E-Cell, the I-Cell, and the D-Node--can be used to design and assemble parallel processing networks for such applications as signal processing and artificial intelligence. The E-Cell (FIG. 1a) is an excitory cell. The I-Cell (FIG. 2a) is an inhibitory cell. The D-Node (FIG. 3) is a combination of E-Cells and I-Cells. The use of the cellular automata is illustrated in three exemplary applications: a lateral inhibition network (FIG. 5b), a tree-search network (FIG. 6b), and a graph-search network (FIG. 7e). In particular, the tree-search and graph-search networks are implemented using the same structure as the tree or graph.
摘要翻译： 一组三个细胞自动机（E-Cell，I-Cell和D-Node）可用于设计和组合用于信号处理和人工智能等应用的并行处理网络。 E细胞（图1a）是一个排泄细胞。 I细胞（图2a）是抑制细胞。 D节点（图3）是E细胞和I细胞的组合。 在三个示例性应用中示出了细胞自动机的使用：横向禁止网络（图5b），树形搜索网络（图6b）和图形搜索网络（图7e）。 特别地，树搜索和图形搜索网络使用与树或图形相同的结构来实现。
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7.发明授权
公开(公告)号：US5390304A
公开(公告)日：1995-02-14
申请号：US590372
申请日：1990-09-28
申请人： Jerald G. Leach , Laurence R. Simar
发明人： Jerald G. Leach , Laurence R. Simar
CPC分类号： G06F9/30043 , G06F9/34 , G06F9/3842 , G06F9/3861
摘要： A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an instruction decode and control unit, having an instruction register operative to hold a program instruction, operative to decode a program instruction providing control signals according to a pipeline organization to control the operations of the data processing device within each instruction cycle and to initiate a block sequence responsive to an instruction code representing a block instruction. A program sequencer circuit, having a program register to hold a program count corresponding to a program address, is operative to access the memory with the contents of the program register to obtain the program instruction corresponding to the program address. Further included is an arithmetic logic unit operative to perform an arithmetic operation on data received by the arithmetic unit and to combine the contents of the program register with a data field decoded from the block instruction by the instruction decode and control unit to generate a block end address, and a block handler unit, having a block start register operative to store the contents of the program register, is responsive to the control signals from the instruction decode and control unit to store the program address corresponding to the block start address to the block start register wherein the contents of the block start register correspond to a start address for a block of instructions to be executed. Other devices, systems and methods are also disclosed.
摘要翻译： 一种数据处理装置，包括用于产生建立指令周期的脉冲的时钟发生器，通过断言地址可访问的存储器，指令解码和控制单元，具有可操作以保存程序指令的指令寄存器，用于解码提供控制信号的程序指令 根据管理组织来控制每个指令周期内的数据处理设备的操作，并且响应于表示块指令的指令代码启动块序列。 具有用于保存与程序地址相对应的程序计数的程序寄存器的程序定序器电路可操作以利用程序寄存器的内容访问存储器，以获得与程序地址相对应的程序指令。 进一步包括的算术逻辑单元可操作以对由算术单元接收的数据进行算术运算，并将程序寄存器的内容与由指令解码和控制单元从块指令解码的数据字段组合，以生成块结束 地址和块处理器单元，具有用于存储程序寄存器的内容的块起始寄存器，响应于来自指令解码和控制单元的控制信号，将对应于块起始地址的程序地址存储到块 起始寄存器，其中块起始寄存器的内容对应于要执行的指令块的起始地址。 还公开了其他装置，系统和方法。
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8.发明授权公开(公告)号：US06625719B2
公开(公告)日：2003-09-23
申请号：US10172590
申请日：2002-06-14
IPC分类号： G06F1200
CPC分类号： G06F9/327 , G06F9/3016 , G06F9/30167 , G06F9/32 , G06F9/321 , G06F9/324 , G06F9/325 , G06F9/342 , G06F9/345 , G06F9/355 , G06F9/3822 , G06F9/3842 , G06F9/3861 , G06F9/3879 , G06F9/3885
摘要： A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data. Further included is an address generating unit connected to the storage circuit, the instruction register, and the address register responsive to the control signals from the instruction decode and control unit combining the initial address word from the address register and the address data from the displacement section to generate a storage circuit address. Other devices, systems and methods are also disclosed.
摘要翻译： 一种数据处理装置，包括通过断言地址可访问的存储电路，连接到存储电路的算术逻辑单元，用于对由算术单元接收的数据执行算术运算。 还包括用于存储表示存储电路地址的初始地址字的地址寄存器。 连接到存储电路并且具有用于保存程序指令的指令寄存器的指令解码和控制单元用于将程序指令解码为控制信号，以控制数据处理设备的操作和位置代码以根据 到所述程序指令的预定部分，其中所述部分中的至少一个包括选择所述地址寄存器的位置部分和包含地址数据的位移部分。 还包括地址生成单元，其响应于来自地址寄存器的初始地址字的指令解码和控制单元的控制信号和来自位移部分的地址数据而连接到存储电路，指令寄存器和地址寄存器 以产生存储电路地址。 还公开了其他装置，系统和方法。
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9.发明授权Microprocessor with a nestable delayed branch instruction without branch related pipeline interlocks 失效具有可分支延迟分支指令的微处理器，无分支相关管道互锁
公开(公告)号：US6055628A
公开(公告)日：2000-04-25
申请号：US12676
申请日：1998-01-23
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3853
摘要： A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ("ALU") L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. These units form an instruction execution pipeline that operates without interlocks so that nestable delayed branch instructions are provided. The control circuitry for the instruction execution pipeline is operable to begin processing a second branch instruction having a second target address on a pipeline phase immediately after beginning processing of a first branch instruction having a first target address. Furthermore, the control circuitry has no interlock or delay circuitry to condition processing of the second branch instruction based on processing of the first branch instruction, therefore the program counter circuitry receives the second target address on a pipeline phase immediately after receiving the first target address regardless of whether the first branch is taken or not. Thus, one instruction may be executed from the first target branch address and then the execution sequence can be preempted to the second target address.
摘要翻译： 微处理器1具有指令提取/解码单元10a-c，多个执行单元，包括算术和加载/存储单元D1，乘法器M1，ALU /移位单元S1，算术逻辑单元（“ALU”） L1，从中读取数据并写入数据的共享多端口寄存器文件20a和存储器22.这些单元形成无互锁操作的指令执行流水线，从而提供可嵌套的延迟分支指令。 用于指令执行流水线的控制电路可操作以在开始处理具有第一目标地址的第一分支指令之后立即开始处理在流水线相位上具有第二目标地址的第二分支指令。 此外，控制电路没有互锁或延迟电路，以基于第一分支指令的处理来调节第二分支指令的处理，因此程序计数器电路在接收到第一目标地址之后立即在流水线阶段上接收第二目标地址 是否采取第一个分支。 因此，可以从第一目标分支地址执行一个指令，然后执行序列可以被抢占到第二目标地址。
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公开(公告)号：US5809309A
公开(公告)日：1998-09-15
申请号：US712244
申请日：1996-09-11
申请人： Jerald G. Leach , Laurence R. Simar
发明人： Jerald G. Leach , Laurence R. Simar
CPC分类号： G06F9/4812 , G06F9/30145 , G06F9/30167 , G06F9/3877
摘要： A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an arithmetic logic unit connected to the memory, operative to perform an arithmetic operation on data received by the arithmetic unit. An instruction decode and control unit connected to the memory, having an instruction register operative to hold a program instruction, is operative to decode a program instruction providing control signals to control the operations of the data processing device and to initiate a interrupt sequence responsive to an instruction code having a interrupt instruction. A program sequencer circuit connected to the memory, having a program register operative to hold a program counter corresponding to a program address is operative to access the memory with the program register to obtain the program instruction corresponding to the program address. A interrupt handler unit, connected to the instruction decode and control unit and the memory, having a hold register operative to store the program register, responsive to the control signals from the instruction decode and control unit to generate an intermediate address to access an interrupt counter from the memory, is operative to store the program register into the hold register and replace the program register with the interrupt counter wherein the interrupt counter corresponds to an address for accessing an interrupt instruction to execute an interrupt routine stored in the memory. Other devices, systems and methods are also disclosed.
摘要翻译： 一种数据处理装置，包括用于产生建立指令周期的脉冲的时钟发生器，通过断言地址可访问的存储器，连接到存储器的算术逻辑单元，用于对由算术单元接收的数据执行算术运算。 连接到具有用于保存程序指令的指令寄存器的存储器的指令解码和控制单元可操作以对提供控制信号的程序指令进行解码，以控制数据处理设备的操作，并响应于 具有中断指令的指令代码。 连接到存储器的程序定序器电路具有用于保存与程序地址相对应的程序计数器的程序寄存器，用于使用程序寄存器访问存储器，以获得与程序地址相对应的程序指令。 连接到指令解码和控制单元和存储器的中断处理单元响应于来自指令解码和控制单元的控制信号产生中间地址以访问中断计数器，具有可操作以存储程序寄存器的保持寄存器 从存储器开始，将程序寄存器存储到保持寄存器中，并且用中断计数器替换程序寄存器，其中中断计数器对应于访问中断指令的地址，以执行存储在存储器中的中断程序。 还公开了其他装置，系统和方法。
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