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1.发明授权公开(公告)号：US06625719B2
公开(公告)日：2003-09-23
申请号：US10172590
申请日：2002-06-14
IPC分类号： G06F1200
CPC分类号： G06F9/327 , G06F9/3016 , G06F9/30167 , G06F9/32 , G06F9/321 , G06F9/324 , G06F9/325 , G06F9/342 , G06F9/345 , G06F9/355 , G06F9/3822 , G06F9/3842 , G06F9/3861 , G06F9/3879 , G06F9/3885
摘要： A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data. Further included is an address generating unit connected to the storage circuit, the instruction register, and the address register responsive to the control signals from the instruction decode and control unit combining the initial address word from the address register and the address data from the displacement section to generate a storage circuit address. Other devices, systems and methods are also disclosed.
摘要翻译： 一种数据处理装置，包括通过断言地址可访问的存储电路，连接到存储电路的算术逻辑单元，用于对由算术单元接收的数据执行算术运算。 还包括用于存储表示存储电路地址的初始地址字的地址寄存器。 连接到存储电路并且具有用于保存程序指令的指令寄存器的指令解码和控制单元用于将程序指令解码为控制信号，以控制数据处理设备的操作和位置代码以根据 到所述程序指令的预定部分，其中所述部分中的至少一个包括选择所述地址寄存器的位置部分和包含地址数据的位移部分。 还包括地址生成单元，其响应于来自地址寄存器的初始地址字的指令解码和控制单元的控制信号和来自位移部分的地址数据而连接到存储电路，指令寄存器和地址寄存器 以产生存储电路地址。 还公开了其他装置，系统和方法。
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2.发明授权Processing devices with improved addressing capabilities, systems and methods 失效具有改进的寻址能力，系统和方法的处理设备
公开(公告)号：US5305446A
公开(公告)日：1994-04-19
申请号：US589968
申请日：1990-09-28
CPC分类号： G06F9/327 , G06F9/3016 , G06F9/30167 , G06F9/32 , G06F9/321 , G06F9/324 , G06F9/325 , G06F9/342 , G06F9/345 , G06F9/355 , G06F9/3822 , G06F9/3842 , G06F9/3861 , G06F9/3879 , G06F9/3885
摘要： A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data. Further included is an address generating unit connected to the storage circuit, the instruction register, and the address register responsive to the control signals from the instruction decode and control unit combining the initial address word from the address register and the address data from the displacement section to generate a storage circuit address. Other devices, systems and methods are also disclosed.
摘要翻译： 一种数据处理装置，包括通过断言地址可访问的存储电路，连接到存储电路的算术逻辑单元，用于对由算术单元接收的数据执行算术运算。 还包括用于存储表示存储电路地址的初始地址字的地址寄存器。 连接到存储电路并且具有用于保存程序指令的指令寄存器的指令解码和控制单元用于将程序指令解码为控制信号，以控制数据处理设备的操作和位置代码以根据 到所述程序指令的预定部分，其中所述部分中的至少一个包括选择所述地址寄存器的位置部分和包含地址数据的位移部分。 还包括地址生成单元，其响应于来自地址寄存器的初始地址字的指令解码和控制单元的控制信号和来自位移部分的地址数据而连接到存储电路，指令寄存器和地址寄存器 以产生存储电路地址。 还公开了其他装置，系统和方法。
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公开(公告)号：US06411984B1
公开(公告)日：2002-06-25
申请号：US09071718
申请日：1998-05-01
IPC分类号： G06F1300
CPC分类号： G06F9/327 , G06F9/3016 , G06F9/30167 , G06F9/32 , G06F9/321 , G06F9/324 , G06F9/325 , G06F9/342 , G06F9/345 , G06F9/355 , G06F9/3822 , G06F9/3842 , G06F9/3861 , G06F9/3879 , G06F9/3885
摘要： A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data. Further included is an address generating unit connected to the storage circuit, the instruction register, and the address register responsive to the control signals from the instruction decode and control unit combining the initial address word from the address register and the address data from the displacement section to generate a storage circuit address. Other devices, systems and methods are also disclosed.
摘要翻译： 一种数据处理装置，包括通过断言地址可访问的存储电路，连接到存储电路的算术逻辑单元，用于对由算术单元接收的数据执行算术运算。 还包括用于存储表示存储电路地址的初始地址字的地址寄存器。 连接到存储电路并且具有用于保存程序指令的指令寄存器的指令解码和控制单元用于将程序指令解码为控制信号，以控制数据处理设备的操作和位置代码以根据 到所述程序指令的预定部分，其中所述部分中的至少一个包括选择所述地址寄存器的位置部分和包含地址数据的位移部分。 还包括地址生成单元，其响应于来自地址寄存器的初始地址字的指令解码和控制单元的控制信号和来自位移部分的地址数据而连接到存储电路，指令寄存器和地址寄存器 以产生存储电路地址。 还公开了其他装置，系统和方法。
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4.发明授权Processing devices with improved addressing capabilities, systems and methods 失效具有改进的寻址能力，系统和方法的处理设备
公开(公告)号：US5751991A
公开(公告)日：1998-05-12
申请号：US420458
申请日：1995-04-10
CPC分类号： G06F9/327 , G06F9/3016 , G06F9/30167 , G06F9/32 , G06F9/321 , G06F9/324 , G06F9/325 , G06F9/342 , G06F9/345 , G06F9/355 , G06F9/3822 , G06F9/3842 , G06F9/3861 , G06F9/3879 , G06F9/3885
摘要： A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data. Further included is an address generating unit connected to the storage circuit, the instruction register, and the address register responsive to the control signals from the instruction decode and control unit combining the initial address word from the address register and the address data from the displacement section to generate a storage circuit address. Other devices, systems and methods are also disclosed.
摘要翻译： 一种数据处理装置，包括通过断言地址可访问的存储电路，连接到存储电路的算术逻辑单元，用于对由算术单元接收的数据执行算术运算。 还包括用于存储表示存储电路地址的初始地址字的地址寄存器。 连接到存储电路并且具有用于保存程序指令的指令寄存器的指令解码和控制单元用于将程序指令解码为控制信号，以控制数据处理设备的操作和位置代码以根据 到所述程序指令的预定部分，其中所述部分中的至少一个包括选择所述地址寄存器的位置部分和包含地址数据的位移部分。 还包括地址生成单元，其响应于来自地址寄存器的初始地址字的指令解码和控制单元的控制信号和来自位移部分的地址数据而连接到存储电路，指令寄存器和地址寄存器 以产生存储电路地址。 还公开了其他装置，系统和方法。
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公开(公告)号：US06374346B1
公开(公告)日：2002-04-16
申请号：US09012326
申请日：1998-01-23
IPC分类号： G06F9302
CPC分类号： G06F9/30094 , G06F9/30101 , G06F9/3842
摘要： A general purpose microprocessor architecture enabling more efficient computations of a type in which Boolean operations and arithmetic operations conditioned on the results of the Boolean operations are interleaved. The microprocessor is provided with a plurality of general purpose registers (“GPRs” 102)and an arithmetic logic unit (“ALU” 104), capable of performing arithmetic operations and Boolean operations. The ALU has a first input (108) and a second input (110), and an output (112), the first and second inputs receiving values stored in the GPRs. The output stores the results of the arithmetic logic unit operations in the GPRs. At least one of the GPRs is capable of receiving directly from the ALU a result of a Boolean operation. In one embodiment, at least one of the GPRs (PN)capable of receiving directly from the ALU a result of a Boolean operation is configured so as to cause the conditioning of an arithmetic operation of the ALU based on the value stored in the GPR.
摘要翻译： 一种通用的微处理器架构，能够更有效地计算一种类型，其中布尔运算和运算布置运算结果的算术运算被交错。 微处理器具有能够执行算术运算和布尔运算的多个通用寄存器（“GPR”102）和算术逻辑单元（“ALU”104）“。 ALU具有第一输入（108）和第二输入（110）以及输出（112），第一和第二输入接收存储在GPR中的值。 输出将算术逻辑单元操作的结果存储在GPR中。 至少有一个GPR能够直接从ALU接收布尔运算的结果。 在一个实施例中，能够直接从ALU接收到布尔运算结果的至少一个GPR（PN）被配置成基于存储在GPR中的值来调节ALU的算术运算。
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6.发明授权Method of returning a data structure from a callee function to a caller function for the C programming language 失效将数据结构从被调用函数返回给C编程语言的调用者函数的方法
公开(公告)号：US5293630A
公开(公告)日：1994-03-08
申请号：US970582
申请日：1992-10-26
申请人： Reid E. Tatge , Alan L. Davis
发明人： Reid E. Tatge , Alan L. Davis
CPC分类号： G06F9/4425
摘要： A method of using a computer to execute a computer program, in which a caller portion of the program calls a callee function that returns a data structure. Before the callee function is called, the computer is used to determine whether the structure is to be used, and if so, an address to which the structure is to be returned is determined. The caller passes this address to the called function. The callee executes, and if the structure is to be used, the callee copies the structure to the predetermined address.
摘要翻译： 一种使用计算机执行计算机程序的方法，其中程序的调用者部分调用返回数据结构的被叫方功能。 在调用被叫功能之前，计算机用于确定是否使用该结构，如果是，则确定要返回结构的地址。 调用者将该地址传递给被叫函数。 被调用者执行，并且如果要使用结构，被叫方将结构复制到预定地址。
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7.发明授权Microprocessor with an instruction immediately next to a branch instruction for adding a constant to a program counter 有权微处理器具有立即在分支指令旁边的指令，用于将常量添加到程序计数器公开(公告)号：US06889320B1
公开(公告)日：2005-05-03
申请号：US09702462
申请日：2000-10-31
CPC分类号： G06F9/30054 , G06F9/30072 , G06F9/30079 , G06F9/30178 , G06F9/321 , G06F9/3802 , G06F9/3842 , G06F9/3853
摘要： A data processing system with a microprocessor that has an instruction execution pipeline that includes fetch and decode stages and several functional execution units. Fetch packets contain a plurality of instruction words. Execution packets include a plurality of instruction words that can be executed in parallel by two or more execution units. An execution packet can span two or more fetch packets. An add (k) constant to program counter (ADDKPC) instruction is provided, such that a parameter specified by the ADDKPC instruction is combined with a value provided by a program counter of microprocessor. The ADDKPC instruction can also specify a number of delay slots after a branch instruction to be filled with virtual NOP instructions such that memory is not wasted with useless NOP instructions. An ADDKPC instruction can provide a relative address for use as a return address. A plurality of predicated ADDKPC instructions can provide a return address selected from a plurality of return addresses. A compiler can reorder code with an ADDKPC instruction to absorb useless NOP instructions.
摘要翻译： 具有微处理器的数据处理系统具有包括读取和解码级的指令执行流水线以及若干功能执行单元。 获取分组包含多个指令字。 执行分组包括可由两个或多个执行单元并行执行的多个指令字。 执行分组可以跨越两个或更多个获取分组。 提供给程序计数器（ADDKPC）指令的add（k）常数，使得由ADDKPC指令指定的参数与由微处理器的程序计数器提供的值组合。 ADDKPC指令还可以指定要在虚拟NOP指令中填充的分支指令之后的多个延迟槽，以使内存不会浪费无用的NOP指令。 ADDKPC指令可以提供用作返回地址的相对地址。 多个预测的ADDKPC指令可以提供从多个返回地址中选择的返回地址。 编译器可以使用ADDKPC指令重新排序代码，以吸收无用的NOP指令。
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8.发明授权Maintaining code consistency among plural instruction sets via function naming convention 失效通过函数命名约定维持多个指令集之间的代码一致性
公开(公告)号：US6002876A
公开(公告)日：1999-12-14
申请号：US938276
申请日：1997-09-26
CPC分类号： G06F8/47 , G06F8/70 , G06F9/4425 , G06F9/45533
摘要： A method of producing a computer program for a computer capable of operating in a plurality of disjoint instruction sets. The method produces a plurality of independently callable functions. For each function the method determines a target instruction set employed by the function. The method provides the function with a name corresponding to the target instruction set. The function name is preferably a modification of a user provided function name corresponding to the target instruction set. The method identifies each call of another independent function and provides each with a name corresponding to the target instruction set. The method produces a veneer function for each function and for each other instruction set. The veneer functions include changing the computer from operating in the other instruction set to operating in the target instruction set, calling the corresponding function, changing the computer to operate in the other instruction set, and a return command. Each veneer function is provided with a name corresponding to the other instruction set. Each function and its corresponding veneer functions are converted into a linkable object code module and then linked into an executable object code file of the computer program. The linker preferably omits from the executable object code file any veneer functions not called by a function.
摘要翻译： 一种用于为能够在多个不相交指令集中操作的计算机产生计算机程序的方法。 该方法产生多个可独立调用的功能。 对于每个函数，该方法确定由该函数使用的目标指令集。 该方法为该函数提供与目标指令集相对应的名称。 功能名称优选地是对应于目标指令集的用户提供的功能名称的修改。 该方法识别另一个独立函数的每个调用，并为每个调用指定与目标指令集相对应的名称。 该方法为每个函数和每个其他指令集生成一个单板函数。 单板功能包括将计算机从另一个指令集中的操作更改为在目标指令集中运行，调用相应功能，将计算机更改为在另一个指令集中操作，以及返回指令。 每个胶合板功能都提供与另一个指令集相对应的名称。 每个函数及其对应的单板函数都被转换成可链接的目标代码模块，然后链接到计算机程序的可执行目标代码文件中。 链接器优选地从可执行对象代码文件中省略未被函数调用的任何单板功能。
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9.发明授权Method and systems for implementing high-radix switch topologies on relatively lower-radix switch physical networks 有权在相对较低的基数交换机物理网络上实现高基数交换机拓扑的方法和系统公开(公告)号：US08774625B2
公开(公告)日：2014-07-08
申请号：US13058024
申请日：2008-08-08
申请人： Nathan L. Binkert , Alan L. Davis , Moray McLaren
发明人： Nathan L. Binkert , Alan L. Davis , Moray McLaren
IPC分类号： H04J14/00
CPC分类号： G02B6/356 , G02B6/02042 , G02B6/3512 , G02B6/3556
摘要： Embodiments of the present invention are directed to implementing high-radix switch topologies on relatively lower-radix physical networks. In one embodiment, the method comprises constructing the physical network (702) composed of one or more optical switches connected via one or more waveguides. A desired switch topology (704) is then designed for implementation on the physical network. The switch topology is then overlain on the switch network by configuring the optical switches and waveguides (706) to implement the switch topology on the physical network. The optical switches can be reconfigured following a transmission over the physical network and can be configured to implement circuit switching or packet switch.
摘要翻译： 本发明的实施例涉及在相对较低基数的物理网络上实现高基数开关拓扑。 在一个实施例中，该方法包括构建由经由一个或多个波导连接的一个或多个光学开关组成的物理网络（702）。 然后设计期望的交换机拓扑（704）以在物理网络上实现。 然后通过配置光开关和波导（706）在开关网络上覆盖开关拓扑以在物理网络上实现开关拓扑。 可以通过物理网络进行传输来重新配置光交换机，并且可以配置为实现电路交换或分组交换。
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公开(公告)号：US4720155A
公开(公告)日：1988-01-19
申请号：US848110
申请日：1986-04-04
申请人： Alan L. Schildkraut , Alan L. Davis
发明人： Alan L. Schildkraut , Alan L. Davis
IPC分类号： H01R13/648 , H05K9/00 , H01R13/658
CPC分类号： H05K9/0007
摘要： An electronic circuit component and a plurality of twinax contacts are connected together in piggy-back fashion and enclosed within a metallic frame with respective signal paths in the component and contacts being interconnected such that an apertured ground plate completes a 360.degree. electrically conductive seal around the contacts and grounds the contacts in common to the metallic frame. The plate also prevents axial leakage of electromagnetic energy from interrupting the electronic component.
摘要翻译： 电子电路部件和多个双芯触点以背对背的方式连接在一起并且封装在金属框架内，并且元件中的相应信号路径被互连，使得有孔接地板在其周围形成360°的导电密封 触点和触点与金属框架共同接触。 该板还防止电磁能量的轴向泄漏中断电子部件。
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