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公开(公告)号：US4518567A
公开(公告)日：1985-05-21
申请号：US416993
申请日：1982-09-13
CPC分类号： C10J3/56 , B01J8/1818 , C10J3/503 , C10J3/74 , C10J3/78 , C10J2300/0959 , C10J2300/0976
摘要： In a reactor for gasification of solid carbonaceous materials in a fluidized bed under elevated pressure and at high temperatures using a hot gasification agent, a feed device for the gasification agent is installed in the lower part of the reactor chamber and traverses this chamber in the form of a bridge, which has an arch joined to the walls of the reactor chamber, said arch consisting of refractory brick and supporting a section of metal pipe. The latter is shielded from the outside by the arch and by a top-mounted structure of refractory material. On the inside, the metal pipe is also provided with a tubular lining of refractory material. Metal pipe, lining, and arch have openings for passage of the gasification agent. The size and shape of the openings are selected to assure passage of the gasification agent even if the parts undergo changes in length as a result of the effects of temperature. The metal pipe section also serves to absorb the forces resulting from the positive pressure of the gasification agent inside it, as well as for the purpose of metering and distributing the gasification agent in the interior of the reactor.
摘要翻译： 在用于在升高的压力和高温下使用热气化剂在流化床中气化固体碳质材料的反应器中，用于气化剂的进料装置安装在反应器室的下部并以这种形式穿过该室 桥梁具有连接到反应室的壁的拱，所述拱由耐火砖组成并且支撑一段金属管。 后者通过拱门和顶部安装的耐火材料结构从外部屏蔽。 在内部，金属管还设置有耐火材料的管状衬里。 金属管，衬里和拱具有用于气化剂通过的开口。 选择开口的尺寸和形状以确保气化剂的通过，即使由于温度的影响，部件长度变化。 金属管部分还用于吸收由其内部的气化剂的正压产生的力，以及用于计量和分配在反应器内部的气化剂的目的。
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2.发明授权Circuit for checking memory cells of programmable MOS-integrated semiconductor memories 失效用于检查可编程MOS集成半导体存储器的存储单元的电路
公开(公告)号：US4458338A
公开(公告)日：1984-07-03
申请号：US290514
申请日：1981-08-06
申请人： Burkhard Giebel , Hans Moormann , Lothar Schrader
发明人： Burkhard Giebel , Hans Moormann , Lothar Schrader
摘要： Circuit arrangement for checking memory cells of programmable MOS-integrated semiconductor memories, especially non-volatile semiconductor memories of the floating-gate type, has an active programming and read mode of operation wherein all word lines of the semiconductor memory with the exception of one selected word line are at a low level. The circuit arrangement also has an inactive power-down mode of operation, wherein all word lines at a high level. Both of the modes of operation are represented by a signal having a first level for the active mode of operation and a second level for the inactive mode of operation. The circuit arrangement further includes a single circuit in the semiconductor memory switchable via a first signal indicating the operating mode for the memory cell test, wherein all of the word lines are addressed by a voltage corresponding to the programming voltage, as a function of a single second signal fed into the semiconductor memory from the outside, from the level indicating the active mode of operation to the level indicating the inactive mode of operation, so that all the word lines can be switched simultaneously to the level required for programming.
摘要翻译： 用于检查可编程MOS集成半导体存储器，特别是浮栅型非易失性半导体存储器的存储单元的电路布置具有有效的编程和读操作模式，其中半导体存储器的所有字线除了一个选定的 字线处于低水平。 电路装置还具有无效的掉电操作模式，其中所有字线处于高电平。 这两种操作模式由具有用于主动操作模式的第一级的信号和用于非活动操作模式的第二级来表示。 该电路装置还包括半导体存储器中的单个电路，其经由指示存储器单元测试的工作模式的第一信号可转换，其中所有字线由与编程电压相对应的电压作为单个电路的函数 第二信号从外部馈送到半导体存储器，从指示活动操作模式的电平到指示不活动操作模式的电平，使得所有字线可以同时切换到编程所需的电平。
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公开(公告)号：US4189737A
公开(公告)日：1980-02-19
申请号：US913827
申请日：1978-06-08
IPC分类号： H01L21/28 , H01L21/336 , H01L29/10 , H01L29/417 , H01L29/78
CPC分类号： H01L29/66484 , H01L21/28273 , H01L29/1033 , H01L29/1045 , H01L29/7831
摘要： A field effect transistor having an extremely short channel length in which a semiconductor substrate of one conductivity type has source and drain zones of the opposite conductivity type. A first gate electrode is separated from the substrate surface by a first insulating layer. The substrate has a surface side counter zone doping extending between the source and drain with the exception of a narrow strip-like zone which directly adjoins the source. The strip-like zone and at least an adjoining part of the surface side counter doped zone is covered by the first gate electrode. A second insulating layer is formed on the first gate electrode and on the drain side edge face of the first gate electrode. A coating on the second insulating layer covering that portion of the first insulating layer not covered by the first gate electrode is formed. The source side edge of the coating determines the drain side boundary of the strip-like zone. The source side edge of the first gate electrode determines the source side boundary of the strip-like semiconductor zone. The first gate electrode is connectable to a control voltage.
摘要翻译： 具有极短沟道长度的场效应晶体管，其中一种导电类型的半导体衬底具有相反导电类型的源区和漏区。 第一栅电极通过第一绝缘层与衬底表面分离。 衬底具有在源极和漏极之间延伸的表面侧反向区域掺杂，除了直接邻接源极的窄带状区域。 带状区域和表面侧反相掺杂区域的至少邻接部分被第一栅电极覆盖。 第二绝缘层形成在第一栅电极和第一栅电极的漏极侧边缘面上。 形成覆盖第一绝缘层未被第一栅电极覆盖的部分的第二绝缘层上的涂层。 涂层的源侧边缘决定了带状区域的漏极边界。 第一栅电极的源极边缘确定条状半导体区的源极边界。 第一栅电极可连接到控制电压。
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4.发明授权Circuit for a read-only memory organized in rows and columns to prevent bit line potentials from dropping 失效用于以列和列组织的只读存储器的电路，以防止位线电位丢失
公开(公告)号：US4435789A
公开(公告)日：1984-03-06
申请号：US290515
申请日：1981-08-06
申请人： Burkhard Giebel , Hans Moormann , Lothar Schrader
发明人： Burkhard Giebel , Hans Moormann , Lothar Schrader
CPC分类号： G11C17/12
摘要： Circuit arrangement for a read-only memory organized in rows and columns, including bit lines having potentials applied thereto, and selection circuits being connected to the bit lines, being addressed by a bit line decoder and containing at least one selection transistor having a cut-off voltage and a gate potential, for preventing bit line potentials from dropping below a given value at which the selection circuits become conducting without having been selected by the bit line decoder, including current-feed lines each being connected to a different one of the bit lines for feeding current to the bit lines and for ensuring that for each of the selection circuits not selected by the bit line decoder the difference between at least one gate potential of the participating selection transistors and the respective bit line potential is smaller than the cut-off voltage of the respective selection transistors.
摘要翻译： 包括以列和列组织的只读存储器的电路布置，包括施加电位的位线和连接到位线的选择电路由位线解码器寻址，并且包含至少一个选择晶体管， 关闭电压和栅极电位，用于防止位线电位降至低于选择电路变为导通的给定值，而不被位线解码器选择，包括各自连接到位的不同位置的电流馈送线 用于将电流馈送到位线的线路，并且为了确保对于未被位线解码器选择的每个选择电路，参与选择晶体管的至少一个栅极电位和相应位线电位之间的差小于切割电位， 各个选择晶体管的截止电压。
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公开(公告)号：US4306352A
公开(公告)日：1981-12-22
申请号：US144896
申请日：1980-04-29
申请人： Lothar Schrader
发明人： Lothar Schrader
IPC分类号： H01L21/28 , H01L21/336 , H01L29/10 , H01L29/417 , H01L29/78 , H01L21/26
CPC分类号： H01L29/66484 , H01L21/28273 , H01L29/1033 , H01L29/78 , H01L29/7831
摘要： A field effect transistor having an extremely short channel length in which a doped semiconductor layer of one conductivity type has oppositely doped source and drain zones in a surface side thereof. A first gate electrode is separated from the semiconductor layer surface by an insulating layer. The first gate electrode covers the region between the source and drain zones with the exception of a strip-like semiconductor region directly adjoining the source zone. A second gate electrode is provided above the strip-like semiconductor region and is insulated from the first gate electrode by a second insulating layer. The first gate electrode is connected to a bias voltage source and the second gate electrode is arranged to be connected to a control voltage.
摘要翻译： 具有极短沟道长度的场效应晶体管，其中一种导电类型的掺杂半导体层在其表面侧具有相反掺杂的源极和漏极区。 第一栅电极通过绝缘层与半导体层表面分离。 第一栅电极覆盖源极和漏极区之间的区域，除了与源极区直接相邻的条状半导体区域之外。 第二栅电极设置在带状半导体区域之上，并通过第二绝缘层与第一栅电极绝缘。 第一栅电极连接到偏置电压源，第二栅极布置成连接到控制电压。
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6.发明授权
公开(公告)号：US4282539A
公开(公告)日：1981-08-04
申请号：US73899
申请日：1979-09-10
申请人： Lothar Schrader
发明人： Lothar Schrader
IPC分类号： H01L29/06 , H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/1033 , H01L29/1041 , H01L29/7838
摘要： An insulated gate field effect transistor has a channel region in a doped semiconductor substrate covered by a thin film region of the insulating layer and has borders defined by thick film regions disposed parallel to the source-drain direction. The transistor further includes a pair of narrow strip zones in the region of the channel borders also running parallel to the source-drain direction which are doped weaker than and oppositely to the substrate doping to partially compensate the substrate doping and in transistors of the depletion type can overcompensate the substrate doping. The compensation provided by the strip zones decreases the substrate control effect so that the effective channel width of the transistor is less susceptible to fluctuations in operating voltages.
摘要翻译： 绝缘栅场效应晶体管在掺杂半导体衬底中具有由绝缘层的薄膜区域覆盖的沟道区域，并且具有由平行于源极 - 漏极方向设置的厚膜区域限定的边界。 晶体管还包括在沟道边界区域中的一对窄带区，其也与平行于源极 - 漏极方向的区域相平行，掺杂比衬底掺杂更弱且相反地掺杂以部分地补偿衬底掺杂，并且在耗尽型晶体管中 可以过度补偿衬底掺杂。 由带区提供的补偿降低了衬底控制效应，使得晶体管的有效沟道宽度不易受到工作电压的波动的影响。
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