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1.发明授权Processor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipeline 失效具有多个执行管线的处理器，使用管段状态信息来控制执行管线的管段之间的指令的独立移动
公开(公告)号：US6138230A
公开(公告)日：2000-10-24
申请号：US902908
申请日：1997-07-29
CPC分类号： G06F9/3861 , G06F9/3838 , G06F9/3853 , G06F9/3867 , G06F9/3875
摘要： A microprocessor comprises a plurality of instruction pipelines having a plurality of stages for processing a stream of instructions, circuitry for simultaneously issuing instructions into two or more of the pipelines without regard to whether one of the simultaneously issued instructions has a data dependency on other of the simultaneously issued instructions, detecting circuitry for detecting dependencies between instructions in the pipelines and circuitry for controlling the flow of instructions through the pipelines such that an instruction is not delayed due to a data dependency on another instruction unless the data dependency must be resolved for proper processing of the instruction in its current stage.
摘要翻译： 微处理器包括具有用于处理指令流的多个级的多条指令流水线，用于同时将指令发布到两条或更多条流水线中的电路，而不考虑同时发出的指令之一是否具有与其他 同时发出的指令，用于检测管道中的指令之间的依赖性的检测电路和用于控制通过管线的指令流的电路，使得由于对另一指令的数据依赖性而不指示指令，否则指令不被延迟，除非必须解决数据依赖性以进行适当的处理 的指示在当前阶段。
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公开(公告)号：US5835949A
公开(公告)日：1998-11-10
申请号：US831842
申请日：1997-04-02
IPC分类号： G06F9/38
CPC分类号： G06F9/3812
摘要： A system and method of readily identifying and handling self-modifying variable length instructions in a pipelined processor is disclosed employing index tags associated with each stage of the execution pipeline wherein the index tags identify the cache line numbers in the instruction cache from which the instructions originate.
摘要翻译： 公开了一种在流水线处理器中容易地识别和处理自修改可变长度指令的系统和方法，其采用与执行流水线的每个级相关联的索引标签，其中索引标签识别指令来自的指令高速缓存中的高速缓存行数 。
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3.发明授权
公开(公告)号：US5644741A
公开(公告)日：1997-07-01
申请号：US138855
申请日：1993-10-18
CPC分类号： G06F9/265 , G06F9/28 , G06F9/30145
摘要： A processor includes storage circuitry for storing an instruction and memory circuitry addressable by a microaddress for outputting a microinstruction in response to the microaddress. The processor further includes sequencing circuitry coupled to provide the microaddress to the memory circuitry. Finally, the processor includes decode circuitry coupled to the storage circuitry for detecting whether the instruction stored in the storage circuitry comprises a single clock instruction before the memory circuit outputs the microinstruction, and for indicating to the sequencing circuitry in response to detecting whether the instruction stored in the storage circuitry comprises a single clock instruction.
摘要翻译： 处理器包括存储电路，用于存储可由微地址寻址的指令和存储器电路，用于响应于微地址输出微指令。 处理器还包括被连接以向存储器电路提供微地址的排序电路。 最后，处理器包括耦合到存储电路的解码电路，用于检测存储在存储电路中的指令是否在存储器电路输出微指令之前包括单个时钟指令，并且响应于检测指令是否存储 在存储电路中包括单个时钟指令。
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4.发明授权In a pipelined processor, setting a segment access indicator during execution stage using exception handling 失效在流水线处理器中，在执行阶段使用异常处理设置段访问指示符
公开(公告)号：US5805879A
公开(公告)日：1998-09-08
申请号：US604788
申请日：1996-02-23
CPC分类号： G06F9/342 , G06F9/30101 , G06F9/30138 , G06F9/3861
摘要： In a pipelined processor having at least one execution pipeline for executing instructions, the execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages, the processor capable of addressing segments of system memory coupled thereto, a circuit for, and method of, setting a segment access indicator associated with a segment of the system memory being accessed by the processor. The circuit includes: (a) exception generating circuitry to generate an exception when the segment access indicator requires setting and (b) exception handling circuitry, invoked by the processor in response to generation of the exception, to flush the execution pipeline of instructions following a segment load instruction, set the segment access indicator and load an address pointer of the processor with an address corresponding to a specified location within the segment.
摘要翻译： 在具有用于执行指令的至少一个执行流水线的流水线处理器中，执行流水线包括ID（解码），AC（地址计算）和EX（执行）处理阶段，处理器能够寻址与其耦合的系统存储器的段， 电路和设置与由处理器访问的系统存储器的段相关联的段访问指示符的方法。 该电路包括：（a）异常产生电路，用于当段访问指示符需要设置时产生异常;以及（b）由处理器响应异常生成而调用的异常处理电路，以刷新指令之后的执行流水线 段加载指令，设置段访问指示符，并加载处理器的地址指针，该地址指针与段内指定位置相对应的地址。
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公开(公告)号：US5596735A
公开(公告)日：1997-01-21
申请号：US606150
申请日：1996-02-23
CPC分类号： G06F9/342 , G06F12/0292
摘要： In a processor having a protected mode of operation in which a computer memory associated with the processor contains global and local descriptor tables addressed by a combination of a base address and an index, the processor having (i) global and local base address registers alternatively to provide the base address and (ii) a selector for containing the index and a table indicator (TI) bit indicating which of the global and local base address registers is to provide the base address, the processor requiring a time to derive the index and a value of the TI bit and a further time to combine the index and the base address, a base address register predicting circuit to predict, and a method of predicting, which of the global and local base address registers is to provide the base address without having to wait for the processor to derive the value of the TI bit. The circuit includes (i) TI bit predicting circuitry to generate a predicted value of the TI bit as a function of a prior value of the TI bit, and (ii) register access circuitry to access one of the global and local base address registers as a function of the predicted value of the TI bit.
摘要翻译： 在具有保护操作模式的处理器中，其中与处理器相关联的计算机存储器包含由基地址和索引的组合寻址的全局和本地描述符表，所述处理器具有（i）全局和本地基地址寄存器， 提供基地址和（ii）用于包含索引的选择器和指示全局和本地基地址寄存器中的哪一个提供基地址的表指示符（TI）位，处理器需要时间来导出索引，以及 TI比特的值以及组合索引和基地址的另外的时间，用于预测的基地址寄存器预测电路和预测全局和本地基地址寄存器中的哪一个将提供基地址而不具有 等待处理器导出TI位的值。 电路包括（i）TI比特预测电路，以产生作为TI比特的先前值的函数的TI比特的预测值，以及（ii）寄存器访问电路以访问全局和本地基地址寄存器之一作为 TI位的预测值的函数。
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6.发明授权Data dependency detection and handling in a microprocessor with write buffer 失效具有写入缓冲器的微处理器中的数据依赖性检测和处理
公开(公告)号：US5471598A
公开(公告)日：1995-11-28
申请号：US139596
申请日：1993-10-18
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3834 , G06F9/3842 , G06F9/3863 , G06F9/3865 , G06F9/3875
摘要： A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.
摘要翻译： 公开了一种具有位于核心和高速缓存之间的写缓冲器的超标量超管道微处理器。 控制写入缓冲器以将写入操作的结果存储到存储器，直到缓存变得可用的时间，例如当不执行高优先级读取时。 写缓冲器包括被分成两个循环缓冲区段的多个条目，以便于与核心的两个管线的交互; 为每个写缓冲区条目提供交叉依赖关系表，以确保以相应部分存在先前数据的可能性，以数据顺序将写入缓冲区写入存储器。 来自存储器的不可缓存读取也按照程序顺序排序，并从写入缓冲区写入数据。 还公开了处理推测执行，检测和处理数据依赖关系和异常以及执行特殊写入功能（未对齐写入和收集的写入）的功能。
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7.发明授权Exception handling for prefetched instruction bytes using valid bits to identify instructions that will cause an exception 失效使用有效位来识别将导致异常的指令的预取指令字节的异常处理
公开(公告)号：US5479616A
公开(公告)日：1995-12-26
申请号：US863226
申请日：1992-04-03
申请人： Raul A. Garibay, Jr. , Mark Bluhm
发明人： Raul A. Garibay, Jr. , Mark Bluhm
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F9/3802
摘要： An exception handling system is used, in an exemplary embodiment, to provide exception handling for prefetched instruction bytes in a pipelined 486-type microprocessor. The microprocessor includes a prefetch unit (22) that controls the loading of a prefetch queue (24), including appending a valid bit to each prefetched instruction byte--this valid bit is conventionally used to notify an instruction decoder (26) that a transferred instruction byte is not valid (such as resulting from a change of flow), causing the decoder to signal a stall condition. According to the exception handling technique of the invention, if the prefetch unit detects that any of a selected number of exception conditions (such as limit violations and page faults) applies to a prefetched instruction byte, it invalidates that instruction byte by clearing the valid bit. When an invalid instruction byte is decoded, the decoder asserts a stall condition that can result from either: (a) the prefetch queue is invalid due to instruction bytes being unavailable or flushing in response to a branch, or (b) an exception condition. An exception processor (30) performs two basic functions: (a) monitoring the prefetch unit, and for any instruction byte for which a potential exception condition exists, storing in an exception status register the associated exception status information (for example, limit violation or page fault), and (b) monitoring the decoder to detect stall conditions. For each stall condition detected, the exception processor checks the exception status register for valid exception status information--if so, it invokes the appropriate exception handling routine. Thus, exception handling occurs at decode time, rather than after execution (requiring instruction abort and side effect handling).
摘要翻译： 在示例性实施例中，使用异常处理系统为流水线486型微处理器中的预取指令字节提供异常处理。 微处理器包括一个预取单元（22），其控制预取队列（24）的加载，包括将有效位附加到每个预取指令字节 - 该有效位通常用于通知指令解码器（26）传送指令 字节无效（例如由于流程的改变而导致的），导致解码器发出失速状态信号。 根据本发明的异常处理技术，如果预取单元检测到选定数量的异常条件（例如限制违规和页面错误）中的任何一个应用于预取指令字节，则通过清除该有效位来使该指令字节无效 。 当无效指令字节被解码时，解码器断言可能由以下原因导致的停顿条件：（a）由于指令字节不可用或响应于分支而刷新，或（b）异常条件，预取队列无效。 异常处理器（30）执行两个基本功能：（a）监视预取单元以及存在潜在异常条件的任何指令字节，在异常状态寄存器中存储关联的异常状态信息（例如，限制违例或 页面故障），（b）监视解码器以检测失速状况。 对于检测到的每个失速条件，异常处理器检查异常状态寄存器以获取有效的异常状态信息 - 如果是，它调用适当的异常处理例程。 因此，异常处理在解码时发生，而不是执行后（需要指令中止和副作用处理）。
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8.发明授权Instruction-initiated method for suspending operation of a pipelined data processor 失效用于暂停流水线数据处理器操作的指令启动方法公开(公告)号：US07509512B2
公开(公告)日：2009-03-24
申请号：US10784702
申请日：2004-02-23
IPC分类号： G06F1/26
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： An instruction-initiated method for suspending operation of a pipelined data processor by selectively disabling a clock signal to pipeline subcircuitry in response to an instruction executed by the pipeline subcircuitry.
摘要翻译： 一种指令启动的方法，用于通过选择性地禁用时钟信号来管理流水线数据处理器，以响应于由管道子电路执行的指令来管理子电路。
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9.发明授权Signal-initiated method for suspending operation of a pipelined data processor 失效用于暂停流水线数据处理器操作的信号发起方法公开(公告)号：US07062666B2
公开(公告)日：2006-06-13
申请号：US10784834
申请日：2004-02-23
IPC分类号： G06F1/26
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： A signal-initiated method for suspending operation of a pipelined data processor by selectively disabling a clock signal to pipeline subcircuitry in response to at least one control signal.
摘要翻译： 一种用于通过响应于至少一个控制信号选择性地禁用时钟信号来流水线分流来暂停流水线数据处理器的操作的信号发起的方法。
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10.发明授权公开(公告)号：US06910141B2
公开(公告)日：2005-06-21
申请号：US10784835
申请日：2004-02-23
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： A pipelined data processor with signal-initiated power management control in which a plurality of subcircuits, including pipeline subcircuitry, and circuitry for generating and controlling at least one clock signal are responsive to at least one control signal by disabling a clock signal to the pipeline subcircuitry.
摘要翻译： 一种具有信号发起的功率管理控制的流水线数据处理器，其中包括管道子电路的多个子电路和用于产生和控制至少一个时钟信号的电路通过禁用到管道子电路的时钟信号来响应于至少一个控制信号 。
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