公开(公告)号：US20070127562A1

公开(公告)日：2007-06-07

申请号：US11297505

申请日：2005-12-07

Applicant: Mark Gehring ,  David Wright

Inventor： Mark Gehring ,  David Wright

IPC: H04B17/00

CPC classification number: H04L1/203 ,  H04B17/318 ,  H04L1/16 ,  H04L2027/0016 ,  H04L2027/002 ,  H04L2027/0034

Abstract: Wireless devices transmit and receive radio signals based upon reference frequencies generated by crystal oscillators. If the reference frequencies of the transmitter and the receiver are different, the radio signals may not be received properly or may not be received at all. A measurement circuit measures the amount of error or signal corruption in the radio signals due to the reference frequency offset between the transmitter and the receiver. A frequency offset circuit generates an offset operating frequency in the transmitter or the receiver to align or calibrate the operating frequencies of the devices.

Abstract translation: 无线设备基于由晶体振荡器产生的参考频率发送和接收无线电信号。 如果发射机和接收机的参考频率不同，则无线电信号可能未被正确接收或根本不被接收。 测量电路测量由于发射机和接收机之间的参考频率偏移导致的无线电信号中的误差或信号损坏量。 频率偏移电路在发射器或接收器中产生偏移操作频率以对准或校准装置的工作频率。

公开(公告)号：US20070082635A1

公开(公告)日：2007-04-12

申请号：US11467346

申请日：2006-08-25

Applicant: Mark Gehring ,  Nathan Moyal

Inventor： Mark Gehring ,  Nathan Moyal

IPC: H04B1/18 ,  H04B7/00 ,  H04B1/06

CPC classification number: H03L7/0802 ,  H03L7/0891 ,  H03L7/14 ,  H03L7/18

Abstract: In a system with an intermittently operating radio, the frequency of which is controlled by a Phase Locked Loop (PLL), a method and system for reducing the power consumed by the PLL by tri-stating the control capacitor in the PLL after the PLL has stabilized at a design frequency. After the capacitor is stabilized, power to some of the components in the PLL is reduced.

Abstract translation: 在具有间歇操作无线电的系统中，其频率由锁相环（PLL）控制，一种用于通过在PLL之后对PLL中的控制电容器进行三态化来降低PLL消耗的功率的方法和系统 稳定在设计频率。 电容器稳定后，PLL中某些组件的电源减少。

公开(公告)号：US07917106B2

公开(公告)日：2011-03-29

申请号：US11669648

申请日：2007-01-31

Applicant: Serge Francois Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Cary Renzema ,  Jeremy Lubkin

Inventor： Serge Francois Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Cary Renzema ,  Jeremy Lubkin

IPC: H04B1/04 ,  H03G3/20

CPC classification number: H03F1/0205 ,  H03F1/0227 ,  H03F1/0238 ,  H03F1/3247 ,  H03F3/24 ,  H03F2200/451 ,  H03F2200/78 ,  H03F2200/99 ,  H03G3/004 ,  H03G3/3042 ,  H04B2001/0408

Abstract: An RF power amplifier system comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal. The phase control loop may comprise one or more variable phase delays introducing a relative phase delay to allow the phase differences between the input and output signals of the PA circuit to be within a range compatible with a phase comparator generating the phase error signal, and a low frequency blocking module that removes the larger extent, lower frequency components of the phase error signal.

Abstract translation: RF功率放大器系统包括幅度控制环路和相位控制环路。 幅度控制环路基于表示输入信号的振幅与输出信号的衰减幅度之间的振幅差的振幅校正信号，调整功率放大器的电源电压。 相位控制环路基于表示输入信号的相位与输出信号的相位差的相位误差信号来调整输入信号的相位。 相位控制回路可以包括引入相对相位延迟的一个或多个可变相位延迟，以允许PA电路的输入和输出信号之间的相位差在与产生相位误差信号的相位比较器兼容的范围内，以及 低频阻塞模块可以消除较大的程度，降低频率分量的相位误差信号。

公开(公告)号：US07432749B1

公开(公告)日：2008-10-07

申请号：US10875667

申请日：2004-06-23

Applicant: Mark Gehring ,  Nathan Moyal

Inventor： Mark Gehring ,  Nathan Moyal

IPC: H03L7/06

CPC classification number: H03L7/10 ,  H03L7/0891 ,  H03L7/18

Abstract: A circuit and method for providing a periodic clock signal, such as a high frequency clock signal. In one example, the circuit may include a phase locked loop circuit having a voltage controlled oscillator, the voltage controlled oscillator having a voltage input, a calibration input, and a clock signal output; and a logic circuit for dynamically calibrating an operating frequency of the phase locked loop during operation of the phase locked loop. In one embodiment, the logic circuit may compare an input voltage into the voltage controlled oscillator against a reference voltage, and if the input voltage is lower than the reference voltage, the logic circuit decreases the operating frequency of the phase locked loop circuit. The logic circuit may compare an input voltage into the voltage controlled oscillator against a reference voltage, and if the input voltage is higher than the reference voltage, the logic circuit increases the operating frequency of the phase locked loop circuit.

Abstract translation: 一种用于提供诸如高频时钟信号的周期性时钟信号的电路和方法。 在一个示例中，电路可以包括具有压控振荡器的锁相环电路，压控振荡器具有电压输入，校准输入和时钟信号输出; 以及用于在锁相环操作期间动态地校准锁相环的工作频率的逻辑电路。 在一个实施例中，逻辑电路可以将参考电压中的压控振荡器的输入电压进行比较，如果输入电压低于参考电压，则逻辑电路降低锁相环电路的工作频率。 逻辑电路可以将压控振荡器的输入电压与参考电压进行比较，如果输入电压高于参考电压，则逻辑电路增加了锁相环电路的工作频率。

公开(公告)号：US20070218848A1

公开(公告)日：2007-09-20

申请号：US11671423

申请日：2007-02-05

Applicant: Serge Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Martin Tomasz

Inventor： Serge Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Martin Tomasz

IPC: H04B1/04 ,  H01Q11/12

CPC classification number: H03F1/0205 ,  H03F1/0227 ,  H03F1/0238 ,  H03F1/3247 ,  H03F2200/451 ,  H03F2200/78 ,  H03F2200/99 ,  H03G3/004 ,  H03G3/3042

Abstract: A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal.

Abstract translation: 一种系统，包括相位比较器，用于比较第一信号和第二信号以产生相位误差信号;以及控制器，响应于所述第一信号中的至少一个的振幅，从所述相位误差信号产生经调整的相位误差信号 和第二个信号。

公开(公告)号：US20070098111A1

公开(公告)日：2007-05-03

申请号：US11261166

申请日：2005-10-27

Applicant: Mark Gehring ,  Russell Moen ,  Brent Jensen

Inventor： Mark Gehring ,  Russell Moen ,  Brent Jensen

IPC: H04L27/12

CPC classification number: H04L27/2092

Abstract: A transmitter digital signal processor (DSP) circuit has a transmit frequency represented by n-bit data output from a look up table (LUT). The n-bit data is outputted to an n-bit accumulator structured to overflow at a rate based on the output n-bit data to output a phase. The circuit further has device structured to add an n-bit signed constant to the accumulator to offset the frequency represented by the n-bit data output from the LUT. A transceiver on a semiconductor chip may include as part of a transmitter circuit, a transmit DSP circuit that has the LUT, accumulator and device providing an n-bit signed constant to the accumulator to offset a transmit frequency in order to allow a receiver circuit on the transceiver to communicate directly with the transmitter circuit, and thus allowing testing of the transceiver.

Abstract translation: 发射机数字信号处理器（DSP）电路具有由查找表（LUT）输出的n位数据表示的发射频率。 n比特数据被输出到构成为以基于输出n比特数据的速率溢出的n比特累加器，以输出相位。 电路还具有被构造为向累加器添加n位有符号常数以便偏移由LUT输出的n位数据表示的频率的器件。 半导体芯片上的收发器可以包括作为发射机电路的一部分的发射DSP电路，其具有LUT，累加器和设备向累加器提供n位有符号常数以偏移发射频率，以允许接收机电路 收发器与发射机电路直接通信，从而允许对收发器进行测试。

公开(公告)号：US20070069928A1

公开(公告)日：2007-03-29

申请号：US11532592

申请日：2006-09-18

Applicant: Mark Gehring ,  Brent Jensen

Inventor： Mark Gehring ,  Brent Jensen

IPC: H03M1/06

CPC classification number: H03D7/1425 ,  H03D7/1433 ,  H03D7/1441 ,  H03D7/1458 ,  H03D2200/0047

Abstract: A circuit including a subcircuit having differential signals, and a feedback circuit coupled to the subcircuit. The feedback circuit is configured to measure an offset between the differential signals, to generate a calibration signal in response to the measurement, and to reduce the offset in response to the calibration signal.

Abstract translation: 包括具有差分信号的分支电路的电路和耦合到子电路的反馈电路。 反馈电路被配置为测量差分信号之间的偏移，以响应于测量而产生校准信号，并且响应于校准信号而减小偏移。

公开(公告)号：US08340604B2

公开(公告)日：2012-12-25

申请号：US13034587

申请日：2011-02-24

Applicant: Serge Francois Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Cary Renzema ,  Jeremy Lubkin

Inventor： Serge Francois Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Cary Renzema ,  Jeremy Lubkin

IPC: H04B1/16

CPC classification number: H03F1/0205 ,  H03F1/0227 ,  H03F1/0238 ,  H03F1/3247 ,  H03F3/24 ,  H03F2200/451 ,  H03F2200/78 ,  H03F2200/99 ,  H03G3/004 ,  H03G3/3042 ,  H04B2001/0408

Abstract: An RF power amplifier system comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal. The phase control loop may comprise one or more variable phase delays introducing a relative phase delay to allow the phase differences between the input and output signals of the PA circuit to be within a range compatible with a phase comparator generating the phase error signal, and a low frequency blocking module that removes the larger extent, lower frequency components of the phase error signal.

Abstract translation: RF功率放大器系统包括幅度控制环路和相位控制环路。 幅度控制环路基于表示输入信号的振幅与输出信号的衰减幅度之间的振幅差的振幅校正信号，调整功率放大器的电源电压。 相位控制环路基于表示输入信号的相位与输出信号的相位差的相位误差信号来调整输入信号的相位。 相位控制回路可以包括引入相对相位延迟的一个或多个可变相位延迟，以允许PA电路的输入和输出信号之间的相位差在与产生相位误差信号的相位比较器兼容的范围内，以及 低频阻塞模块可以消除较大的程度，降低频率分量的相位误差信号。

公开(公告)号：US20110140777A1

公开(公告)日：2011-06-16

申请号：US13034587

申请日：2011-02-24

Applicant: Serge Francois Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Cary Renzema ,  Jeremy Lubkin

Inventor： Serge Francois Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Cary Renzema ,  Jeremy Lubkin

IPC: H03G3/20

CPC classification number: H03F1/0205 ,  H03F1/0227 ,  H03F1/0238 ,  H03F1/3247 ,  H03F3/24 ,  H03F2200/451 ,  H03F2200/78 ,  H03F2200/99 ,  H03G3/004 ,  H03G3/3042 ,  H04B2001/0408

Abstract: An RF power amplifier system comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal. The phase control loop may comprise one or more variable phase delays introducing a relative phase delay to allow the phase differences between the input and output signals of the PA circuit to be within a range compatible with a phase comparator generating the phase error signal, and a low frequency blocking module that removes the larger extent, lower frequency components of the phase error signal.

Abstract translation: RF功率放大器系统包括幅度控制环路和相位控制环路。 幅度控制环路基于表示输入信号的振幅与输出信号的衰减幅度之间的振幅差的振幅校正信号，调整功率放大器的电源电压。 相位控制环路基于表示输入信号的相位与输出信号的相位差的相位误差信号来调整输入信号的相位。 相位控制回路可以包括引入相对相位延迟的一个或多个可变相位延迟，以允许PA电路的输入和输出信号之间的相位差在与产生相位误差信号的相位比较器兼容的范围内，以及 低频阻塞模块可以消除较大的程度，降低频率分量的相位误差信号。

公开(公告)号：US20070184794A1

公开(公告)日：2007-08-09

申请号：US11669648

申请日：2007-01-31

Applicant: Serge Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Cary Renzema ,  Jeremy Lubkin

Inventor： Serge Drogi ,  Vikas Vinayak ,  Mark Gehring ,  Cary Renzema ,  Jeremy Lubkin

IPC: H04B1/04 ,  H01Q11/12

CPC classification number: H03F1/0205 ,  H03F1/0227 ,  H03F1/0238 ,  H03F1/3247 ,  H03F3/24 ,  H03F2200/451 ,  H03F2200/78 ,  H03F2200/99 ,  H03G3/004 ,  H03G3/3042 ,  H04B2001/0408

Abstract: An RF power amplifier system comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal. The phase control loop may comprise one or more variable phase delays introducing a relative phase delay to allow the phase differences between the input and output signals of the PA circuit to be within a range compatible with a phase comparator generating the phase error signal, and a low frequency blocking module that removes the larger extent, lower frequency components of the phase error signal.

Abstract translation: RF功率放大器系统包括幅度控制环路和相位控制环路。 幅度控制环路基于表示输入信号的振幅与输出信号的衰减幅度之间的振幅差的振幅校正信号，调整功率放大器的电源电压。 相位控制环路基于表示输入信号的相位与输出信号的相位差的相位误差信号来调整输入信号的相位。 相位控制回路可以包括引入相对相位延迟的一个或多个可变相位延迟，以允许PA电路的输入和输出信号之间的相位差在与产生相位误差信号的相位比较器兼容的范围内，以及 低频阻塞模块可以消除较大的程度，降低频率分量的相位误差信号。