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1.发明授权RF power amplifier controller circuit including calibrated phase control loop 有权RF功率放大器控制器电路包括校准相位控制回路公开(公告)号：US07917106B2
公开(公告)日：2011-03-29
申请号：US11669648
申请日：2007-01-31
CPC分类号： H03F1/0205 , H03F1/0227 , H03F1/0238 , H03F1/3247 , H03F3/24 , H03F2200/451 , H03F2200/78 , H03F2200/99 , H03G3/004 , H03G3/3042 , H04B2001/0408
摘要： An RF power amplifier system comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal. The phase control loop may comprise one or more variable phase delays introducing a relative phase delay to allow the phase differences between the input and output signals of the PA circuit to be within a range compatible with a phase comparator generating the phase error signal, and a low frequency blocking module that removes the larger extent, lower frequency components of the phase error signal.
摘要翻译： RF功率放大器系统包括幅度控制环路和相位控制环路。 幅度控制环路基于表示输入信号的振幅与输出信号的衰减幅度之间的振幅差的振幅校正信号，调整功率放大器的电源电压。 相位控制环路基于表示输入信号的相位与输出信号的相位差的相位误差信号来调整输入信号的相位。 相位控制回路可以包括引入相对相位延迟的一个或多个可变相位延迟，以允许PA电路的输入和输出信号之间的相位差在与产生相位误差信号的相位比较器兼容的范围内，以及 低频阻塞模块可以消除较大的程度，降低频率分量的相位误差信号。
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2.发明授权RF power amplifier controller circuit including calibrated phase control loop 有权RF功率放大器控制器电路包括校准相位控制回路公开(公告)号：US08340604B2
公开(公告)日：2012-12-25
申请号：US13034587
申请日：2011-02-24
IPC分类号： H04B1/16
CPC分类号： H03F1/0205 , H03F1/0227 , H03F1/0238 , H03F1/3247 , H03F3/24 , H03F2200/451 , H03F2200/78 , H03F2200/99 , H03G3/004 , H03G3/3042 , H04B2001/0408
摘要： An RF power amplifier system comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal. The phase control loop may comprise one or more variable phase delays introducing a relative phase delay to allow the phase differences between the input and output signals of the PA circuit to be within a range compatible with a phase comparator generating the phase error signal, and a low frequency blocking module that removes the larger extent, lower frequency components of the phase error signal.
摘要翻译： RF功率放大器系统包括幅度控制环路和相位控制环路。 幅度控制环路基于表示输入信号的振幅与输出信号的衰减幅度之间的振幅差的振幅校正信号，调整功率放大器的电源电压。 相位控制环路基于表示输入信号的相位与输出信号的相位差的相位误差信号来调整输入信号的相位。 相位控制回路可以包括引入相对相位延迟的一个或多个可变相位延迟，以允许PA电路的输入和输出信号之间的相位差在与产生相位误差信号的相位比较器兼容的范围内，以及 低频阻塞模块可以消除较大的程度，降低频率分量的相位误差信号。
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3.发明申请RF Power Amplifier Controller Circuit Including Calibrated Phase Control Loop 有权包括校准相位控制回路的RF功率放大器控制器电路公开(公告)号：US20110140777A1
公开(公告)日：2011-06-16
申请号：US13034587
申请日：2011-02-24
IPC分类号： H03G3/20
CPC分类号： H03F1/0205 , H03F1/0227 , H03F1/0238 , H03F1/3247 , H03F3/24 , H03F2200/451 , H03F2200/78 , H03F2200/99 , H03G3/004 , H03G3/3042 , H04B2001/0408
摘要： An RF power amplifier system comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal. The phase control loop may comprise one or more variable phase delays introducing a relative phase delay to allow the phase differences between the input and output signals of the PA circuit to be within a range compatible with a phase comparator generating the phase error signal, and a low frequency blocking module that removes the larger extent, lower frequency components of the phase error signal.
摘要翻译： RF功率放大器系统包括幅度控制环路和相位控制环路。 幅度控制环路基于表示输入信号的振幅与输出信号的衰减幅度之间的振幅差的振幅校正信号，调整功率放大器的电源电压。 相位控制环路基于表示输入信号的相位与输出信号的相位差的相位误差信号来调整输入信号的相位。 相位控制回路可以包括引入相对相位延迟的一个或多个可变相位延迟，以允许PA电路的输入和输出信号之间的相位差在与产生相位误差信号的相位比较器兼容的范围内，以及 低频阻塞模块可以消除较大的程度，降低频率分量的相位误差信号。
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4.发明申请RF Power Amplifier Controller Circuit Including Calibrated Phase Control Loop 有权包括校准相位控制回路的RF功率放大器控制器电路公开(公告)号：US20070184794A1
公开(公告)日：2007-08-09
申请号：US11669648
申请日：2007-01-31
申请人： Serge Drogi , Vikas Vinayak , Mark Gehring , Cary Renzema , Jeremy Lubkin
发明人： Serge Drogi , Vikas Vinayak , Mark Gehring , Cary Renzema , Jeremy Lubkin
CPC分类号： H03F1/0205 , H03F1/0227 , H03F1/0238 , H03F1/3247 , H03F3/24 , H03F2200/451 , H03F2200/78 , H03F2200/99 , H03G3/004 , H03G3/3042 , H04B2001/0408
摘要： An RF power amplifier system comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal. The phase control loop may comprise one or more variable phase delays introducing a relative phase delay to allow the phase differences between the input and output signals of the PA circuit to be within a range compatible with a phase comparator generating the phase error signal, and a low frequency blocking module that removes the larger extent, lower frequency components of the phase error signal.
摘要翻译： RF功率放大器系统包括幅度控制环路和相位控制环路。 幅度控制环路基于表示输入信号的振幅与输出信号的衰减幅度之间的振幅差的振幅校正信号，调整功率放大器的电源电压。 相位控制环路基于表示输入信号的相位与输出信号的相位差的相位误差信号来调整输入信号的相位。 相位控制回路可以包括引入相对相位延迟的一个或多个可变相位延迟，以允许PA电路的输入和输出信号之间的相位差在与产生相位误差信号的相位比较器兼容的范围内，以及 低频阻塞模块可以消除较大的程度，降低频率分量的相位误差信号。
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公开(公告)号：US20230208432A1
公开(公告)日：2023-06-29
申请号：US17561136
申请日：2021-12-23
申请人： Fabrice Paillet , Jason Muhlestein , James Keith Hodgson , SHIVADARSHAN BIDADI RAJEURS , George Matthew , Anand Ramasundar , Cary Renzema , Po-Cheng Chen , Sergio Carlo Rodriguez , Seng Rou Tey
发明人： Fabrice Paillet , Jason Muhlestein , James Keith Hodgson , SHIVADARSHAN BIDADI RAJEURS , George Matthew , Anand Ramasundar , Cary Renzema , Po-Cheng Chen , Sergio Carlo Rodriguez , Seng Rou Tey
CPC分类号： H03M1/785 , H02M3/157 , H02M1/0025
摘要： An apparatus, system, and method for digital-to-analog (converter) control are provided. A DAC includes a first resistor ladder including a plurality of first electrical taps into different portions of the first resistor ladder, first and second pass gate trees coupled to receive outputs from the first electrical taps, first and second buffers coupled to receive outputs from the first and second pass gate trees, respectively, a second resistor ladder coupled to receive and be biased by outputs of the first and second buffers, the second resistor ladder including a plurality of second electrical taps into different portions of the second resistor ladder, and third, fourth, and fifth pass gate trees coupled to receive outputs from the second electrical taps.
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公开(公告)号：US20230092022A1
公开(公告)日：2023-03-23
申请号：US17483381
申请日：2021-09-23
申请人： Fabrice Paillet , Anand Ramasundar , Khondker Ahmed , Harish K. Krishnamurthy , Cary Renzema , Christopher Mandic , James Keith Hodgson
发明人： Fabrice Paillet , Anand Ramasundar , Khondker Ahmed , Harish K. Krishnamurthy , Cary Renzema , Christopher Mandic , James Keith Hodgson
IPC分类号： G05F1/56
摘要： An apparatus, system, and method for voltage regulator (VR) control are provided. An apparatus can include first, second, and third comparators configured to determine whether a load voltage (VLOAD) drops below a lower non-linear control (NLC) threshold, drops below a lower linear control (LC) threshold, and exceeds an upper LC threshold, respectively. The apparatus can include power gates (PGs) configured to adjust an output voltage (VOUT) based on a provided power gate (PG) code. The apparatus can include voltage regulator (VR) controller circuitry comprising synchronous LC circuitry and asynchronous NLC circuitry, the LC circuitry configured to increment or decrement the PG code responsive to the VLOAD dropping below the LC threshold and exceeding the upper LC threshold, respectively, and the NLC circuitry configured to increase the PG code based on a number of consecutive NLC droop events and responsive to the VLOAD dropping below the lower NLC threshold.
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公开(公告)号：US20220113751A1
公开(公告)日：2022-04-14
申请号：US17645896
申请日：2021-12-23
申请人： James Keith Hodgson , Fabrice Paillet , Christopher J. Mandic , Cary Renzema , Anand Ramasundar , Sami Hyvonen , Po-Cheng Chen , Alex Santiago Rodriguez , Sergio Carlo Rodriguez , Saravanan Ramamoorthy , Ruthvin Jeevan Suvarna
发明人： James Keith Hodgson , Fabrice Paillet , Christopher J. Mandic , Cary Renzema , Anand Ramasundar , Sami Hyvonen , Po-Cheng Chen , Alex Santiago Rodriguez , Sergio Carlo Rodriguez , Saravanan Ramamoorthy , Ruthvin Jeevan Suvarna
IPC分类号： G05F1/46
摘要： A reduced-size replica of power gate transistors may be used within a closed-loop voltage regulator to measure the average current delivered by the transistors in the non-replica power gate. The measured current is compared against a known reference current, and a feedback loop is used to modify the gate bias of the power gate and replica power gate transistors. An improved current sensing power gate replica solution may include measuring current from a small replica of the power gate and extrapolating the total current by digitally multiplying the replica current by the ratio of the size of the enabled power gates to the size of the replicas. The current through the replicas, which substantially matches the current in equivalent power gate devices, may be collected on an analog bus and conducted across a known resistor to generate a voltage that determines an estimated current of the power gate devices.
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