公开(公告)号：US09177087B1

公开(公告)日：2015-11-03

申请号：US13289785

申请日：2011-11-04

Applicant: Masashi Shimanouchi ,  Peng Li ,  Daniel Tun Lai Chow

Inventor： Masashi Shimanouchi ,  Peng Li ,  Daniel Tun Lai Chow

IPC: G06G7/48 ,  G06F17/50 ,  G06G7/63

CPC classification number: G06F17/5036 ,  G06F17/5068 ,  G06F2217/82 ,  G06G7/63

Abstract: One embodiment relates to a method of generating worst case inter-symbol interference (ISI) inducing short patterns for simulating and/or testing a communication link. The method includes the generation of a binary clock sequence comprising bits of alternating values at the beginning of the pattern. In addition, an ISI inducing binary sequences and its complement are generated after the clock sequence. Another embodiment relates to a pattern generator for generating an worst case inter-symbol interference inducing short pattern for testing a communication link. Other embodiments, aspects, and features are also disclosed.

Abstract translation: 一个实施例涉及产生用于模拟和/或测试通信链路的短模式的最差情况符号间干扰（ISI）的方法。 该方法包括生成在图案开始处包含交替值的位的二进制时钟序列。 此外，在时钟序列之后产生ISI诱导二进制序列及其补码。 另一实施例涉及用于产生用于测试通信链路的最坏情况的符号间干扰诱导短模式的模式发生器。 还公开了其它实施例，方面和特征。

公开(公告)号：US20250023959A1

公开(公告)日：2025-01-16

申请号：US18900217

申请日：2024-09-27

Applicant: Hsinho Wu ,  Masashi Shimanouchi ,  Peng Li

Inventor： Hsinho Wu ,  Masashi Shimanouchi ,  Peng Li

IPC: H04L69/18

Abstract: Integrated circuit devices, methods, and circuitry to enable a higher-power transceiver to comply with a lower-power protocol. An integrated circuit system may include a first transceiver to operate using a first protocol and multi-protocol adapter circuitry. The multi-protocol adapter circuitry may be configurable to enable the first transceiver to be compliant with a second protocol that is a lower-power protocol than the first protocol.

公开(公告)号：US20230094919A1

公开(公告)日：2023-03-30

申请号：US17483771

申请日：2021-09-23

Applicant: Hsinho Wu ,  Peng Li ,  Masashi Shimanouchi

Inventor： Hsinho Wu ,  Peng Li ,  Masashi Shimanouchi

IPC: H04L1/20 ,  H04L1/00

Abstract: Various embodiments provide apparatuses, systems, and methods to determine a figure of merit (FOM) of a communication link (e.g., a serial communication link, also referred to herein as a channel) between a transmitter and a receiver. The FOM may be used to, for example, determine a health of the communication link during mission mode (normal operating mode), determine a modulation scheme to use for the communication link, determine a configuration to use for the receiver and/or transmitter, and/or another suitable use case. Other embodiments may be described and claimed.

公开(公告)号：US20210328852A1

公开(公告)日：2021-10-21

申请号：US17358982

申请日：2021-06-25

Applicant: Masashi Shimanouchi ,  Hsinho Wu ,  Peng Li

Inventor： Masashi Shimanouchi ,  Hsinho Wu ,  Peng Li

IPC: H04L27/36 ,  H04L27/38

Abstract: Systems and devices are provided for receiving or transmitting IQ data (e.g., suitable for passband quadrature amplitude modulation (QAM)) over a wireline using pairs of baseband pulse amplitude modulation (PAM-n) signals. Encoding circuitry may map data from an input bit stream to IQ data that includes an in-phase component and a quadrature-phase component. Modulator circuitry may determine an in-phase PAM-n signal based on the in-phase component and a quadrature-phase PAM-n signal based on the quadrature-phase component. Driver circuitry may transmit the in-phase PAM-n signal and the quadrature-phase PAM-n signal across a wireline channel. The in-phase PAM-n signal may be different by 90° from the quadrature-phase PAM-n signal. This may enable a remote receiver on the wireline channel to detect the in-phase PAM-n signal independently of the quadrature-phase PAM-n signal.

公开(公告)号：US20130195155A1

公开(公告)日：2013-08-01

申请号：US13363098

申请日：2012-01-31

Applicant: Mingde PAN ,  Weiqi DING ,  Sergey SHUMARAYEV ,  Peng LI ,  Masashi SHIMANOUCHI

Inventor： Mingde PAN ,  Weiqi DING ,  Sergey SHUMARAYEV ,  Peng LI ,  Masashi SHIMANOUCHI

IPC: H04L25/10 ,  H04B1/38

CPC classification number: H04L25/4917 ,  H03D1/00 ,  H04L25/066 ,  H04L27/06

Abstract: One embodiment relates to a receiver circuit for multi-level amplitude signaling which includes at least three amplitude levels for each symbol period. The receiver circuit includes a peak detector, a reference voltage generator, and a comparator circuit. The peak detector is arranged to detect a peak voltage of the multi-level amplitude signal, and the reference voltage generator uses the peak voltage to generate multiple reference voltages. The comparator circuit uses the multiple reference voltages to detect an amplitude level of the multi-level amplitude signal. Other embodiments and features are also disclosed.

Abstract translation: 一个实施例涉及用于多电平振幅信令的接收机电路，其包括用于每个符号周期的至少三个幅度电平。 接收器电路包括峰值检测器，参考电压发生器和比较器电路。 峰值检测器被设置为检测多电平幅度信号的峰值电压，并且参考电压发生器使用峰值电压来产生多个参考电压。 比较器电路使用多个参考电压来检测多电平幅度信号的幅度电平。 还公开了其它实施例和特征。

公开(公告)号：US20110257953A1

公开(公告)日：2011-10-20

申请号：US12762848

申请日：2010-04-19

Applicant: Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

Inventor： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

Abstract translation: 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。 链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

公开(公告)号：US09222972B1

公开(公告)日：2015-12-29

申请号：US12884747

申请日：2010-09-17

Applicant: Weiqi Ding ,  Sergey Shumarayev ,  Mingde Pan ,  Peng Li ,  Masashi Shimanouchi

Inventor： Weiqi Ding ,  Sergey Shumarayev ,  Mingde Pan ,  Peng Li ,  Masashi Shimanouchi

IPC: G01R31/02 ,  G01R31/317

CPC classification number: G01R31/31709

Abstract: An IC that includes a jitter generator, where the jitter generator is integral with the IC and generates non-intrinsic jitter, is provided. In one implementation, the non-intrinsic jitter is used to measure a characteristic of the IC. In one implementation, the non-intrinsic jitter is used to test jitter tolerance of the IC. In yet another implementation, the non-intrinsic jitter is used to test another IC coupled to the IC that includes the jitter generator.

Abstract translation: 提供了包括抖动发生器的IC，其中抖动发生器与IC集成并产生非固有抖动。 在一个实现中，非固有抖动用于测量IC的特性。 在一个实现中，非固有抖动用于测试IC的抖动容限。 在又一实现中，使用非固有抖动来测试耦合到包括抖动发生器的IC的另一IC。

公开(公告)号：US07615990B1

公开(公告)日：2009-11-10

申请号：US11824333

申请日：2007-06-28

Applicant: Masashi Shimanouchi

Inventor： Masashi Shimanouchi

IPC: G01R31/02

CPC classification number: G01R31/31926

Abstract: An enhanced loadboard and method for enhanced automated test equipment (ATE) signaling. More specifically, embodiments provide an effective mechanism for reducing signal degradation and error interjection by replacing one or more relays with signal splitters for directing signals between one or more pins of a coupled ATE instrument, where the signal splitters reduce loadboard size and operating cost.

Abstract translation: 增强的自动测试设备（ATE）信号的加载板和方法。 更具体地，实施例提供了一种用于通过用信号分离器替换一个或多个继电器来降低信号劣化和误差的有效机构，用于在耦合的ATE仪器的一个或多个引脚之间引导信号，其中信号分离器减小了负载板尺寸和操作成本。

公开(公告)号：US06859902B1

公开(公告)日：2005-02-22

申请号：US09679042

申请日：2000-10-02

Applicant: Wajih Dalal ,  Masashi Shimanouchi ,  Robert J. Glenn ,  Burnell G. West

Inventor： Wajih Dalal ,  Masashi Shimanouchi ,  Robert J. Glenn ,  Burnell G. West

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/319 ,  G01R31/3193

CPC classification number: G01R31/3171 ,  G01R31/2884 ,  G01R31/31709 ,  G01R31/31905 ,  G01R31/31926 ,  G01R31/31937

Abstract: A testing method and circuit used to test high-speed communication devices on Automatic Test Equipment—ATE. The method and circuit provide a solution to testing very high speed (2.5 Gbps and above) integrated circuits. The circuit fans out the data streams from the output of the Device Under Test (DUT) to multiple tester channels which under-sample the streams. The testing method and circuit also allow for the injection of jitter into to the DUT at the output of the DUT. The skipping of data bits inherent in multi-pass testing is avoided by duplicating the tester resources to achieve effective real-time capture (saving test time and improving Bit Error Rate). Moreover the circuit synchronizes different DUTs with the timing of ATE hardware independent of DUT output data. Also, a calibration method is used compensate for differing trace lengths and propagation delay characteristics of test circuit components.

Abstract translation: 用于测试自动测试设备-ATE上的高速通信设备的测试方法和电路。 该方法和电路提供了测试非常高速（2.5Gbps及以上）集成电路的解决方案。 该电路将数据流从被测器件（DUT）的输出中排除到多个测试器通道，这些通道对流进行了低采样。 测试方法和电路还允许在DUT的输出端将抖动注入DUT。 通过复制测试人员资源实现有效的实时捕获（节省测试时间和提高误码率），可以避免多遍测试中固有的数据位的跳过。 此外，该电路将不同的DUT与ATE硬件的定时同步，与DUT的输出数据无关。 此外，使用校准方法来补偿测试电路部件的不同迹线长度和传播延迟特性。

公开(公告)号：US08626474B2

公开(公告)日：2014-01-07

申请号：US12762848

申请日：2010-04-19

Applicant: Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

Inventor： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

IPC: G06F7/60 ,  G06G7/62 ,  G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

Abstract translation: 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。 链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。