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23 条记录 (耗时 0.018 秒)

    Semiconductor integrated circuit device
    1.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US08884375B2

    公开(公告)日：2014-11-11

    申请号：US12561719

    申请日：2009-09-17

    申请人： Satoshi Nakai ,  Masato Suga ,  Jusuke Ogura

    发明人： Satoshi Nakai ,  Masato Suga ,  Jusuke Ogura

    IPC分类号： H01L29/76 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L21/02225 ,  H01L21/8238 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/7843

    摘要： A disclosed semiconductor integrated circuit device includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.

    摘要翻译： 所公开的半导体集成电路器件包括半导体衬底; 以及设置在半导体衬底上的多个半导体元件。 半导体元件包括n沟道MOS晶体管和p沟道MOS晶体管。 n沟道MOS晶体管由拉伸应力膜覆盖，并且p沟道MOS晶体管被压缩应力膜覆盖。 在半导体衬底的表面上设置整个表面被拉伸应力膜和压缩应力膜的组合覆盖的虚拟区域。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    2.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20100001350A1

    公开(公告)日：2010-01-07

    申请号：US12561719

    申请日：2009-09-17

    申请人： Satoshi Nakai ,  Masato Suga ,  Jusuke Ogura

    发明人： Satoshi Nakai ,  Masato Suga ,  Jusuke Ogura

    IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/302

    CPC分类号： H01L21/02225 ,  H01L21/8238 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/7843

    摘要： A disclosed semiconductor integrated circuit device includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.

    摘要翻译： 所公开的半导体集成电路器件包括半导体衬底; 以及设置在半导体衬底上的多个半导体元件。 半导体元件包括n沟道MOS晶体管和p沟道MOS晶体管。 n沟道MOS晶体管由拉伸应力膜覆盖，并且p沟道MOS晶体管被压缩应力膜覆盖。 在半导体衬底的表面上设置整个表面被拉伸应力膜和压缩应力膜的组合覆盖的虚拟区域。

    Semiconductor device having a guard ring
    3.
    发明授权
    Semiconductor device having a guard ring 有权
    具有保护环的半导体器件

    公开(公告)号：US07256474B2

    公开(公告)日：2007-08-14

    申请号：US10777189

    申请日：2004-02-13

    申请人： Shigetoshi Wakayama ,  Mutsuaki Kai ,  Hiroyuki Kato ,  Masato Suga

    发明人： Shigetoshi Wakayama ,  Mutsuaki Kai ,  Hiroyuki Kato ,  Masato Suga

    IPC分类号： H01L23/544

    CPC分类号： H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A multilayer interconnection structure of a semiconductor device includes a first guard ring extending continuously along a periphery of a substrate and a second guard ring extending continuously in the multilayer interconnection structure along the periphery so as to be encircled by the first guard ring and so as to encircle an interconnection pattern inside the multilayer interconnection structure, wherein the first and second guard rings are connected with each other mechanically and continuously by a bridging conductor pattern extending continuously in a band form along a region including the first and second guard rings when viewed in the direction perpendicular to the substrate.

    摘要翻译： 半导体器件的多层互连结构包括沿着衬底的周边连续延伸的第一保护环和沿着周边在多层互连结构中连续延伸的第二保护环，以便被第一保护环包围，从而 围绕所述多层互连结构内部的互连图案，其中所述第一和第二保护环通过桥接导体图案彼此机械连续地连接，所述桥接导体图案沿着包括所述第一和第二保护环的区域以带状连续延伸， 垂直于衬底的方向。

    Semiconductor integrated circuit device having diagonal direction wiring and layout method therefor
    4.
    发明申请
    Semiconductor integrated circuit device having diagonal direction wiring and layout method therefor 有权

    公开(公告)号：US20070117231A1

    公开(公告)日：2007-05-24

    申请号：US11653261

    申请日：2007-01-16

    申请人： Masato Suga

    发明人： Masato Suga

    IPC分类号： H01L21/66 ,  H01L23/48

    CPC分类号： G06F17/5077 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device having a plurality of circuit elements and a plurality of wires connecting the circuit elements, includes an orthogonal wire having a first minimum wire width which is formed on a first wiring layer and extends horizontally or vertically; a diagonal wire having a second minimum wire width which is substantially equal to the first minimum wire width, formed on a second wiring layer which differs from the first wiring layer and extending in a diagonal direction in relation to the orthogonal wire; and a via having a size which is no greater than the first or second wire width, formed at point at which the orthogonal wire and diagonal wire overlap so as to connect the orthogonal wire and diagonal wire, wherein one of the diagonal wire and orthogonal wire includes an enlarged wire width region in the position at which the via is formed, the wire width of the enlarged wire width region being enlarged beyond the first or second minimum wire width.

    Semiconductor integrated circuit device having diagonal direction wiring and layout method therefor
    5.
    发明授权
    Semiconductor integrated circuit device having diagonal direction wiring and layout method therefor 有权

    公开(公告)号：US07183659B2

    公开(公告)日：2007-02-27

    申请号：US11338822

    申请日：2006-01-25

    申请人： Masato Suga

    发明人： Masato Suga

    IPC分类号： H01L23/48

    CPC分类号： G06F17/5077 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device having a plurality of circuit elements and a plurality of wires connecting the circuit elements, includes an orthogonal wire having a first minimum wire width which is formed on a first wiring layer and extends horizontally or vertically; a diagonal wire having a second minimum wire width which is substantially equal to the first minimum wire width, formed on a second wiring layer which differs from the first wiring layer and extending in a diagonal direction in relation to the orthogonal wire; and a via having a size which is no greater than the first or second wire width, formed at point at which the orthogonal wire and diagonal wire overlap so as to connect the orthogonal wire and diagonal wire, wherein one of the diagonal wire and orthogonal wire includes an enlarged wire width region in the position at which the via is formed, the wire width of the enlarged wire width region being enlarged beyond the first or second minimum wire width.

    Fuse and method for disconnecting the fuse
    10.
    发明申请
    Fuse and method for disconnecting the fuse 审中-公开
    熔断器和断路保险丝的方法

    公开(公告)号：US20070090486A1

    公开(公告)日：2007-04-26

    申请号：US11336829

    申请日：2006-01-23

    申请人： Satoshi Otsuka ,  Toyoji Sawada ,  Masato Suga ,  Jun Nagayama ,  Motonobu Sato ,  Takashi Suzuki

    发明人： Satoshi Otsuka ,  Toyoji Sawada ,  Masato Suga ,  Jun Nagayama ,  Motonobu Sato ,  Takashi Suzuki

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The fuse comprises an interconnection part 14 luding a silicon layer; a contact part 20b connected one end of the interconnection part 14; and a contact part 20aconnected to the other end of the interconnection part 14 and containing a metal material. A current is flowed from the contact part 20bto the contact part 20a to migrate the metal material of the contact part 20a to the silicon layer to thereby change the contact resistance between the interconnection part 14 and the contact part 20a.

    摘要翻译： 保险丝包括一个布置硅层的互连部分14; 连接互连部分14的一端的接触部分20b; 以及连接到互连部分14的另一端并包含金属材料的接触部分。 电流从接触部分20b流到接触部分20a，以将接触部分20a的金属材料迁移到硅层，从而改变互连部分14和接触部分20a之间的接触电阻。