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18 条记录 (耗时 0.015 秒)

    Device for maintaining the oscillation of a balance for a timepiece
    8.
    发明授权
    Device for maintaining the oscillation of a balance for a timepiece 失效
    用于维持钟表的平衡振荡的装置

    公开(公告)号：US4011714A

    公开(公告)日：1977-03-15

    申请号：US558857

    申请日：1975-03-17

    申请人： Tsutomu Ishizuka ,  Seiji Ichikawa

    发明人： Tsutomu Ishizuka ,  Seiji Ichikawa

    IPC分类号： G04C3/06 ,  G04C3/04

    CPC分类号： G04C3/069

    摘要： The device comprises a balance having two magnets attached thereto, a coil combining pick-up and driving functions, two complementary transistors, an RC circuit formed of a speed-up first condenser and a first resistor, a biasing second resistor, a coupling second condenser a third resistor and a third condenser. This device is capable of operating over a wide temperature range, is less influenced by the deviation generally seen in the commercially available transistors, is simplified in construction, is inexpensive to manufacture and is adapted for mass production.

    摘要翻译： 该装置包括具有附接到其上的两个磁体的平衡，组合拾取和驱动功能的线圈，两个互补晶体管，由加速第一电容器和第一电阻器形成的RC电路，偏置第二电阻器，耦合第二电容器 第三电阻器和第三电容器。 该器件能够在宽的温度范围内工作，受市售晶体管中普遍看到的偏差的影响较小，结构简单，制造成本低廉，适用于批量生产。

    Field-effect transistor, semiconductor chip and semiconductor device
    9.
    发明申请
    Field-effect transistor, semiconductor chip and semiconductor device 失效
    场效晶体管，半导体芯片和半导体器件

    公开(公告)号：US20090078966A1

    公开(公告)日：2009-03-26

    申请号：US12232788

    申请日：2008-09-24

    申请人： Shuji Asai ,  Akira Fujihara ,  Makoto Matsunoshita ,  Naoki Sakura ,  Seiji Ichikawa

    发明人： Shuji Asai ,  Akira Fujihara ,  Makoto Matsunoshita ,  Naoki Sakura ,  Seiji Ichikawa

    IPC分类号： H01L29/778 ,  H01L23/48

    CPC分类号： H01L29/7783 ,  H01L29/66462 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/12032 ,  H01L2924/13062 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A FET exhibiting excellent uniformity and productivity and having a low noise figure and high associated gain as high-frequency performance, a semiconductor chip having this FET and a semiconductor device having the semiconductor chip. The FET includes a GaAs substrate on which are built up an i-type GaAs layer, an i-type InGaAs two-dimensional electron gas layer and an n-type AlGaAs electron supply layer. A gate electrode is provided on and in linear Schottky contact with the n-type AlGaAs electron supply layer. A n-type InGaP etching stop layer and then an n-type GaAs contact layer at the same lateral position are built up on the n-type AlGaAs electron supply layer, these being spaced away from both sides of the gate electrode. A source electrode and a drain electrode are provided on the n-type GaAs contact layer and are spaced away from edges of the contact layer as electrodes that make band-shaped ohmic contact.

    摘要翻译： 具有优异的均匀性和生产率并且具有低噪声系数和高相关增益作为高频性能的FET，具有该FET的半导体芯片和具有半导体芯片的半导体器件。 该FET包括GaAs衬底，其上构建有i型GaAs层，i型InGaAs二维电子气体层和n型AlGaAs电子供应层。 栅电极设置在与n型AlGaAs电子供应层的线性肖特基接触中。 在n型AlGaAs电子供给层上形成n型InGaP蚀刻停止层，然后在同一横向位置形成n型GaAs接触层，这些与栅电极的两侧间隔开。 源电极和漏电极设置在n型GaAs接触层上，并且与接触层的边缘间隔开，作为带状欧姆接触的电极。

    Method of producing a semiconductor device
    10.
    发明授权
    Method of producing a semiconductor device 失效
    半导体装置的制造方法

    公开(公告)号：US06467666B2

    公开(公告)日：2002-10-22

    申请号：US09870299

    申请日：2001-05-30

    申请人： Seiji Ichikawa ,  Tatsuo Tokue ,  Nobuo Nagano ,  Fumie Ogihara ,  Taku Sato

    发明人： Seiji Ichikawa ,  Tatsuo Tokue ,  Nobuo Nagano ,  Fumie Ogihara ,  Taku Sato

    IPC分类号： B65H2300

    CPC分类号： H01L21/67092 ,  B28D5/0011 ,  H01L21/3043 ,  H01L21/78 ,  H05K1/0306 ,  H05K3/0052 ,  H05K2201/09036 ,  H05K2201/0909 ,  H05K2203/1572 ,  H05K2203/302 ,  Y10T225/12 ,  Y10T225/325

    摘要： A method of producing a semiconductor device of the present invention is applicable to a multilayer wafer for leadless chip carrier packages and breaks it on a package basis. The method begins with a step of forming a generally V-shaped groove in one major surfaces of the wafer in the direction of thickness of the wafer. A weak, cleaving portion is formed in the other major surface of the wafer in alignment with the groove. A cleaving force is exerted on the wafer to thereby form a break in the cleaving portion, so that the wafer is caused to break from the groove toward the cleaving portion in the direction of thickness of the wafer. The cleaving portion may be replaced with a strong, non-cleaving portion, in which case the break is formed in the interface between the non-cleaving portion and the wafer due to a difference in cleaving force.

    摘要翻译： 本发明的半导体器件的制造方法可应用于无引线芯片载体封装的多层晶片，并以封装为基础将其破坏。 该方法开始于在晶片的一个主表面上沿晶片厚度方向形成大致V形槽的步骤。 在晶片的另一个主表面上与凹槽对准地形成弱的分离部分。 切割力施加在晶片上，从而在裂开部分形成断裂，从而使得晶片在晶片的厚度方向上从凹槽向分裂部分断裂。 切割部分可以用强的非分裂部分代替，在这种情况下，由于分裂力的差异，在非裂开部分和晶片之间的界面中形成断裂。