公开(公告)号：US20140065832A1

公开(公告)日：2014-03-06

申请号：US13602697

申请日：2012-09-04

申请人： Chi-Wen Hsieh ,  Chi-Kang Chang ,  Chia-Chu Liu ,  Meng-Wei Chen ,  Kuei-Shun Chen

发明人： Chi-Wen Hsieh ,  Chi-Kang Chang ,  Chia-Chu Liu ,  Meng-Wei Chen ,  Kuei-Shun Chen

IPC分类号： H01L21/308 ,  H01L23/544

CPC分类号： H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L27/0883 ,  H01L27/0886 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

摘要： An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.

摘要翻译： 公开了适用于制造非平面电路器件的重叠标记和形成覆盖标记的方法。 示例性实施例包括接收具有有源器件区域和覆盖区域的衬底。 在基板上形成一个或多个电介质层和硬掩模。 图案化硬掩模以形成被配置为限定覆盖标记鳍的硬掩模层特征。 间隔物形成在图案化的硬掩模层上。 垫片进一步限定重叠标记鳍片和有源器件鳍片。 覆盖标记鳍被切割以形成用于定义覆盖度量的参考位置的鳍线端。 蚀刻电介质层和衬底以进一步限定覆盖标记鳍。

公开(公告)号：US20130280909A1

公开(公告)日：2013-10-24

申请号：US13451605

申请日：2012-04-20

申请人： Yuan-Hsiang Lung ,  Kuei-Shun Chen ,  Meng-Wei Chen ,  Chia-Ying Lee

发明人： Yuan-Hsiang Lung ,  Kuei-Shun Chen ,  Meng-Wei Chen ,  Chia-Ying Lee

IPC分类号： H01L21/306 ,  G03F1/70

CPC分类号： H01L21/31144 ,  G03F1/70 ,  H01L21/76816

摘要： A method for optimizing masks used for forming conductive features and a method for creating the mask features on an IC device are disclosed. An exemplary embodiment includes receiving a design database including a plurality of conductive features. First and second features suitable for joining are identified from the plurality of conductive features. A joined feature corresponding to the first and the second features is characterized. A cut shape configured to separate the first and second features from the joined feature is also characterized. The joined feature is categorized into a first conductive mask, the cut shape is categorized into a cut mask, and a third feature is categorized into a second conductive mask. The categorized shapes and features of the first conductive mask, the second conductive mask, and the cut mask are provided for manufacturing a mask set corresponding to the categorized shapes and features.

摘要翻译： 公开了一种用于优化用于形成导电特征的掩模的方法和用于在IC器件上产生掩模特征的方法。 示例性实施例包括接收包括多个导电特征的设计数据库。 从多个导电特征中识别适合于接合的第一和第二特征。 表征与第一和第二特征对应的连接特征。 被配置为将第一和第二特征与接合的特征分离的切割形状也被表征。 连接的特征被分类为第一导电掩模，切割形状被分为切割掩模，第三特征被分类为第二导电掩模。 提供第一导电掩模，第二导电掩模和切割掩模的分类形状和特征，用于制造对应于分类形状和特征的掩模组。

公开(公告)号：US20130095662A1

公开(公告)日：2013-04-18

申请号：US13276168

申请日：2011-10-18

申请人： Chia-Chu Liu ,  Kuei Shun Chen ,  Meng Wei Chen

发明人： Chia-Chu Liu ,  Kuei Shun Chen ,  Meng Wei Chen

IPC分类号： H01L21/312 ,  G06F17/50

CPC分类号： H01L21/3086 ,  H01L21/31144 ,  H01L27/0207

摘要： The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules; and complex features as a second layout wherein the second layout violates the design rules. The method further includes generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features.

摘要翻译： 本公开提供了集成电路（IC）设计方法的一个实施例。 该方法包括接收具有多个IC特征的IC设计布局。 该方法包括从IC设计布局识别作为第一布局的简单特征，其中第一布局不违反设计规则; 以及作为第二布局的复杂特征，其中第二布局违反了设计规则。 该方法还包括从第二布局生成第三布局和第四布局，其中第三布局包括复杂特征和连接特征以满足设计规则，并且第四布局包括修剪特征。

公开(公告)号：US07097945B2

公开(公告)日：2006-08-29

申请号：US10249559

申请日：2003-04-18

申请人： Ching-Yu Chang ,  Hsin-huei Chen ,  Meng-Wei Chen

发明人： Ching-Yu Chang ,  Hsin-huei Chen ,  Meng-Wei Chen

IPC分类号： G03F1/00 ,  H01L21/302

CPC分类号： G03F1/70

摘要： A method of reducing a critical dimension (“CD”) bias between a dense pattern and an isolation pattern is disclosed. The method includes a first step of providing a mask having a dense pattern, an isolation pattern and the other area of the mask is transparent, in which mask the dense pattern has a first opaque pattern and the isolation pattern has a second opaque pattern. The second step of the method is forming a virtual pattern around the isolation pattern, in which a distance between the virtual pattern and the isolation pattern is y, and the virtual pattern has a pattern line width x. By forming the virtual pattern around the isolation pattern, the flare effect of the isolation pattern is close to that of the dense pattern, thus the CD bias between a dense pattern, and an isolation pattern is reduced, and the process window does not shrink.

摘要翻译： 公开了一种降低致密图案和隔离图案之间的临界尺寸（“CD”）偏压的方法。 该方法包括提供具有致密图案的掩模，隔离图案和掩模的另一区域是透明的第一步骤，其中密集图案具有第一不透明图案，并且隔离图案具有第二不透明图案。 该方法的第二步是在隔离图案周围形成虚拟图案，其中虚拟图案和隔离图案之间的距离为y，虚拟图案具有图案线宽度x。 通过在隔离图案周围形成虚拟图案，隔离图案的耀斑效应接近密集图案的闪光效果，因此减小密集图案和隔离图案之间的CD偏差，并且处理窗口不缩小。

公开(公告)号：US08850369B2

公开(公告)日：2014-09-30

申请号：US13451605

申请日：2012-04-20

申请人： Yuan-Hsiang Lung ,  Kuei-Shun Chen ,  Meng-Wei Chen ,  Chia-Ying Lee

发明人： Yuan-Hsiang Lung ,  Kuei-Shun Chen ,  Meng-Wei Chen ,  Chia-Ying Lee

IPC分类号： G06F17/50

CPC分类号： H01L21/31144 ,  G03F1/70 ,  H01L21/76816

摘要： A method for optimizing masks used for forming conductive features and a method for creating the mask features on an IC device are disclosed. An exemplary embodiment includes receiving a design database including a plurality of conductive features. First and second features suitable for joining are identified from the plurality of conductive features. A joined feature corresponding to the first and the second features is characterized. A cut shape configured to separate the first and second features from the joined feature is also characterized. The joined feature is categorized into a first conductive mask, the cut shape is categorized into a cut mask, and a third feature is categorized into a second conductive mask. The categorized shapes and features of the first conductive mask, the second conductive mask, and the cut mask are provided for manufacturing a mask set corresponding to the categorized shapes and features.

摘要翻译： 公开了一种用于优化用于形成导电特征的掩模的方法和用于在IC器件上产生掩模特征的方法。 示例性实施例包括接收包括多个导电特征的设计数据库。 从多个导电特征中识别适合于接合的第一和第二特征。 表征与第一和第二特征对应的连接特征。 被配置为将第一和第二特征与接合的特征分离的切割形状也被表征。 连接的特征被分类为第一导电掩模，切割形状被分为切割掩模，第三特征被分类为第二导电掩模。 提供第一导电掩模，第二导电掩模和切割掩模的分类形状和特征，用于制造对应于分类形状和特征的掩模组。

公开(公告)号：US08562843B2

公开(公告)日：2013-10-22

申请号：US13276168

申请日：2011-10-18

申请人： Chia-Chu Liu ,  Kuei Shun Chen ,  Meng Wei Chen

发明人： Chia-Chu Liu ,  Kuei Shun Chen ,  Meng Wei Chen

IPC分类号： H01B13/00

CPC分类号： H01L21/3086 ,  H01L21/31144 ,  H01L27/0207

摘要： The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules; and complex features as a second layout wherein the second layout violates the design rules. The method further includes generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features.

摘要翻译： 本公开提供了集成电路（IC）设计方法的一个实施例。 该方法包括接收具有多个IC特征的IC设计布局。 该方法包括从IC设计布局识别作为第一布局的简单特征，其中第一布局不违反设计规则; 以及作为第二布局的复杂特征，其中第二布局违反了设计规则。 该方法还包括从第二布局生成第三布局和第四布局，其中第三布局包括复杂特征和连接特征以满足设计规则，并且第四布局包括修剪特征。

公开(公告)号：US08237297B2

公开(公告)日：2012-08-07

申请号：US12835415

申请日：2010-07-13

申请人： Kuei Shun Chen ,  Meng-Wei Chen ,  George Liu ,  Jiann Yuan Huang ,  Chia-Ching Lin

发明人： Kuei Shun Chen ,  Meng-Wei Chen ,  George Liu ,  Jiann Yuan Huang ,  Chia-Ching Lin

IPC分类号： H01L23/544

CPC分类号： G03F9/7084 ,  G03F9/7076 ,  G03F9/708 ,  H01L21/76229

摘要： The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a substrate having a device region and an alignment region; a first shallow trench isolation (STI) feature in the alignment region and having a first depth D1; a second STI feature in the device region and having a second depth D2; an alignment mark with patterned features overlying the first STI in the alignment region; and a gate stack formed on an active region in the device region.

摘要翻译： 对准标记及其制作方法进行说明。 在一个实施例中，半导体结构包括具有器件区域和对准区域的衬底; 在对准区域中的第一浅沟槽隔离（STI）特征并且具有第一深度D1; 在设备区域中具有第二深度D2的第二STI特征; 具有覆盖对准区域中的第一STI的图案特征的对准标记; 以及形成在器件区域中的有源区上的栅极堆叠。

公开(公告)号：US08203836B2

公开(公告)日：2012-06-19

申请号：US12696306

申请日：2010-01-29

申请人： Hsin-Chih Chen ,  Yun-Chung Chang ,  Hsin-Chi Huang ,  Meng-Wei Chen ,  Li-Wen Hsu ,  Ju-I Lee

发明人： Hsin-Chih Chen ,  Yun-Chung Chang ,  Hsin-Chi Huang ,  Meng-Wei Chen ,  Li-Wen Hsu ,  Ju-I Lee

IPC分类号： G06F1/16

CPC分类号： G06F1/181

摘要： A cover structure is disposed at the electronic device. The electronic device includes a frame with an opening and a power supply. The cover structure includes a cover and a pivotal portion. The cover includes an inner surface, an outer surface, and a touch portion. The pivotal portion includes a pivotal part and a trigger. The pivotal part is located on the inner surface. The trigger is located at the opening of the frame and connected with the pivotal part. The touch portion corresponds to the opening. When the touch portion is pressed, the pivotal part drives the trigger to trigger the power supply to drive the electronic device.

摘要翻译： 盖结构设置在电子设备上。 电子设备包括具有开口和电源的框架。 盖结构包括盖和枢转部分。 盖包括内表面，外表面和触摸部分。 枢转部分包括枢转部分和触发器。 枢轴部分位于内表面。 触发器位于框架的开口处并与枢转部分连接。 触摸部分对应于开口。 当按压触摸部分时，枢转部分驱动触发器以触发电源以驱动电子设备。

公开(公告)号：US20120038021A1

公开(公告)日：2012-02-16

申请号：US12854660

申请日：2010-08-11

申请人： Meng-Wei Chen ,  Chi-Chuang Lee ,  Chung-Hsien Lin

发明人： Meng-Wei Chen ,  Chi-Chuang Lee ,  Chung-Hsien Lin

IPC分类号： H01L23/544 ,  H01L29/06 ,  G03F7/20 ,  H01L21/02

CPC分类号： G03F7/70633 ,  G03F9/7076 ,  G03F9/7084 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and apparatuses for alignment are disclosed. An exemplary method includes providing a substrate having a device region and an alignment region; forming a first material layer over the substrate; forming a device feature and a dummy feature in the first material layer, wherein the device feature is formed in the device region and the dummy feature is formed in the alignment region; forming a second material layer over the first material layer; and forming an alignment feature in the second material layer, the alignment feature being disposed over the dummy feature in the alignment region. The device feature has a first dimension and the dummy feature has a second dimension, the second dimension being less than a resolution of an alignment mark detector

摘要翻译： 公开了用于对准的方法和装置。 一种示例性方法包括提供具有器件区域和对准区域的衬底; 在所述衬底上形成第一材料层; 在所述第一材料层中形成器件特征和虚拟特征，其中所述器件特征形成在所述器件区域中，并且所述伪特征形成在所述对准区域中; 在所述第一材料层上形成第二材料层; 以及在所述第二材料层中形成对准特征，所述对准特征被布置在所述对准区域中的所述虚拟特征之上。 设备特征具有第一维度，虚拟特征具有第二维度，第二维度小于对准标记检测器的分辨率

公开(公告)号：US08822343B2

公开(公告)日：2014-09-02

申请号：US13602697

申请日：2012-09-04

申请人： Chi-Wen Hsieh ,  Chi-Kang Chang ,  Chia-Chu Liu ,  Meng-Wei Chen ,  Kuei-Shun Chen

发明人： Chi-Wen Hsieh ,  Chi-Kang Chang ,  Chia-Chu Liu ,  Meng-Wei Chen ,  Kuei-Shun Chen

IPC分类号： H01L21/308

CPC分类号： H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L27/0883 ,  H01L27/0886 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

摘要： An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.

摘要翻译： 公开了适用于制造非平面电路器件的重叠标记和形成覆盖标记的方法。 示例性实施例包括接收具有有源器件区域和覆盖区域的衬底。 在基板上形成一个或多个电介质层和硬掩模。 图案化硬掩模以形成被配置为限定覆盖标记鳍的硬掩模层特征。 间隔物形成在图案化的硬掩模层上。 垫片进一步限定重叠标记鳍片和有源器件鳍片。 覆盖标记鳍被切割以形成用于定义覆盖度量的参考位置的鳍线端。 蚀刻电介质层和衬底以进一步限定覆盖标记鳍。