公开(公告)号：US20130176052A1

公开(公告)日：2013-07-11

申请号：US13345564

申请日：2012-01-06

Applicant: Michael D. Hutton ,  David Lewis

Inventor： Michael D. Hutton ,  David Lewis

IPC: H03K19/177

CPC classification number: H03K19/17764 ,  H03K19/17736

Abstract: An integrated circuit may include programmable logic regions coupled in parallel to an interconnect bus. Multiplexing circuitry may be interposed between the programmable logic regions and the interconnect bus. The multiplexing circuitry may be formed from multiplexing circuits formed in a cascade structure. The multiplexing circuitry may dynamically receive control signals that determines which programmable logic region is allowed to drive output signals onto the interconnect bus. Alternatively, each programmable logic region may have an associated output circuit that is coupled to the interconnect bus. The output circuits may be dynamically controlled by control circuitry. The output circuits may receive control signals from the control circuitry that selectively enable and selectively disable the output circuits. The output circuits may be formed with logic circuitry that ensures that the interconnect bus is not simultaneously driven by the output circuits.

Abstract translation: 集成电路可以包括与互连总线并联耦合的可编程逻辑区域。 多路复用电路可以插在可编程逻辑区和互连总线之间。 复用电路可以由级联结构中形成的多路复用电路形成。 复用电路可以动态地接收控制信号，该控制信号确定允许哪个可编程逻辑区域将输出信号驱动到互连总线上。 或者，每个可编程逻辑区域可以具有耦合到互连总线的相关联的输出电路。 输出电路可以由控制电路动态控制。 输出电路可以接收来自控制电路的控制信号，其选择性地启用和选择性地禁用输出电路。 输出电路可以由确保互连总线不由输出电路同时驱动的逻辑电路形成。

公开(公告)号：US20130009666A1

公开(公告)日：2013-01-10

申请号：US13613925

申请日：2012-09-13

Applicant: Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

Inventor： Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

IPC: H03K19/177

CPC classification number: H03K19/17744 ,  H03K19/17732 ,  H03K19/17796

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract translation: 提供具有集成专用集成电路（ASIC）结构的现场可编程门阵列（FPGA）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由自定义区域和接口区域组成。 定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。 定制区域可以基于结构化ASIC设计。 接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

公开(公告)号：US08314636B2

公开(公告)日：2012-11-20

申请号：US12767696

申请日：2010-04-26

Applicant: Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

Inventor： Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

IPC: H03K19/177

CPC classification number: H03K19/17744 ,  H03K19/17732 ,  H03K19/17796

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract translation: 提供具有集成专用集成电路（ASIC）结构的现场可编程门阵列（FPGA）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由自定义区域和接口区域组成。 定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。 定制区域可以基于结构化ASIC设计。 接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

公开(公告)号：US08112728B1

公开(公告)日：2012-02-07

申请号：US12539070

申请日：2009-08-11

Applicant: Michael D. Hutton ,  David Karchmer

Inventor： Michael D. Hutton ,  David Karchmer

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5036 ,  G06F17/5031

Abstract: A performance estimation module estimates the performance values of user designs in early phases of compilation and accounts for the performance variability introduced by subsequent compilation phases. The user design is parameterized. The performance estimation model outputs a probability distribution function of estimated performance values of the user design, based upon this parameterization. The performance estimation model is created by parameterizing sample designs. The sample designs are compiled and analyzed to determine their performance values. To account for random variability in compilation phases, the module compiles and analyzes sample designs multiple times. The performance estimation model is created from the relationship between sample designs' performance values and their parameterizations. A regression analysis may be used to determine this relationship. The performance estimation model can be updated with the analysis of compiled user designs. The performance values can include timing, power, and resource consumption.

Abstract translation: 性能估计模块在编译的早期阶段估计用户设计的性能价值，并考虑随后编译阶段引入的性能变异性。 用户设计参数化。 基于该参数化，性能估计模型输出用户设计的估计性能值的概率分布函数。 通过参数化样本设计创建性能估计模型。 样本设计被编译和分析以确定其性能值。 为了解决编译阶段的随机变化，模块多次对样本进行编译和分析。 性能估计模型是根据样本设计的性能值与参数化之间的关系来创建的。 可以使用回归分析来确定这种关系。 可以通过编译用户设计的分析来更新性能估计模型。 性能值可以包括时序，功率和资源消耗。

公开(公告)号：US07784008B1

公开(公告)日：2010-08-24

申请号：US11330931

申请日：2006-01-11

Applicant: Michael D. Hutton ,  David Karchmer ,  Zhiru Zhang

Inventor： Michael D. Hutton ,  David Karchmer ,  Zhiru Zhang

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054 ,  G06F2217/08 ,  G06F2217/78 ,  G06F2217/84

Abstract: A visualization displays user designs and performance information at different levels of detail. Related register bits are combined into a metaregister and displayed as a graph node. The set of paths and associated combinatorial logic between two or more metaregisters are collapsed into a metapath and displayed as a graph connection. The set of paths associated with a metapath can be selectively revealed in response to user input. Metapaths can be annotated with performance information of its associated paths, such as timing, area, and power consumption information. The annotated performance information can represent performance information of one or more paths or aggregate attributes of the set of paths. Paths associated with control signals and finite state machines can be identified and displayed as separate graph connections.

Abstract translation: 可视化显示不同级别的用户设计和性能信息。 相关寄存器位组合成一个表示器并显示为一个图形节点。 一组路径和相关联的组合逻辑在两个或更多的metaregister之间折叠成元路径并显示为一个图连接。 可以响应于用户输入而选择性地显示与元路径相关联的路径集合。 Metapaths可以用其相关路径的性能信息（如时序，区域和功耗信息）进行注释。 注释的性能信息可以表示路径集合的一个或多个路径或聚合属性的性能信息。 与控制信号和有限状态机相关联的路径可以被识别并显示为单独的图形连接。

公开(公告)号：US07579866B1

公开(公告)日：2009-08-25

申请号：US11479311

申请日：2006-06-30

Applicant: Michael D. Hutton ,  David Cashman ,  Jinyoung Yuan ,  Kimberly Anne Bozman

Inventor： Michael D. Hutton ,  David Cashman ,  Jinyoung Yuan ,  Kimberly Anne Bozman

IPC: H03K19/173 ,  H01L25/00

CPC classification number: H03K19/17748 ,  H03K19/17736

Abstract: A programmable logic device architecture providing efficient configurable functionality to allow the “tie-off” of logic region-wide control signals. This functionality is provided while maintaining the efficiency of region-wide signals, yet allows sufficient flexibility for effective use of register-packing and usage within the region. Methods are given for both sub-region and individual logic element tie-off granularity. In various embodiments, the tie-off logic may be used for logic wide signals used in PLDs having logic elements arranged in regions of logic, sometimes referred to in the industry as either Logic Array Blocks or Complex Logic Blocks.

Abstract translation: 提供有效配置功能的可编程逻辑器件架构，以允许逻辑区域范围的控制信号的“关联”。 在保持区域范围信号的效率的同时提供这一功能，但是为了有效利用区域内的寄存器封装和使用提供了足够的灵活性。 给出了子区域和单个逻辑元素绑定粒度的方法。 在各种实施例中，关联逻辑可以用于具有布置在逻辑区域中的逻辑元件的PLD中的逻辑宽信号，在逻辑区域中有时被称为逻辑阵列块或复杂逻辑块。

公开(公告)号：US20090051387A1

公开(公告)日：2009-02-26

申请号：US11894283

申请日：2007-08-20

Applicant: Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

Inventor： Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

IPC: H03K19/177

CPC classification number: H03K19/17744 ,  H03K19/17732 ,  H03K19/17796

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract translation: 提供了具有集成专用集成电路（“ASIC”）结构的现场可编程门阵列（“FPGA”）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由“自定义区域”和“接口区域”组成。 定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。 定制区域可以基于结构化ASIC设计。 接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

公开(公告)号：US20080290898A1

公开(公告)日：2008-11-27

申请号：US12125824

申请日：2008-05-22

Applicant: Michael D. HUTTON

Inventor： Michael D. HUTTON

IPC: H03K19/177

CPC classification number: H03K19/17728

Abstract: A CLB-based PLD with logic cells having improved logic, register, arithmetic, logic packing and timing functions and capabilities is disclosed. The CLBs of the PLD are arranged in rows and columns of an array and are interconnect by a plurality of interconnect lines. Each of the plurality of CLBs has a first slice of logic cells and a second slice of logic cells arranged in a first column and a second column. First and second carry chains are provided between each of the logic cells of each column. At least one of the logic cells includes one or more Look Up Tables for implanting logic functions on a set of inputs provided to the one logic cell and an arithmetic logic circuit configured to receive a carry-in signal and to generate a carry-out signal forming part of the first carry chain. In one embodiment, the logic cell further includes a first output register and a second output register and the set of outputs generated by the logic cell are partitioned among the first output register and the second output register. In another embodiment, an output of one of the registers is provided as an input to one of the Look Up Tables of the cell through a register feedback connection. In yet another embodiment, the set of inputs provided to a first and a second of the Look Up Tables are different, enabling a higher degree of logic efficiency or “packing” by enabling each cell to perform logic functions on two different sets of inputs as opposed to only the same set of inputs. Finally, in another embodiment, the arithmetic logic circuit is capable of generating two SUM output signals.

Abstract translation: 公开了具有逻辑单元的具有改进的逻辑，寄存器，算术，逻辑封装和定时功能和能力的基于CLB的PLD。 PLD的CLB被布置成阵列的行和列，并且通过多条互连线互连。 多个CLB中的每一个具有布置在第一列和第二列中的逻辑单元的第一切片和逻辑单元的第二切片。 在每列的每个逻辑单元之间提供第一和第二进位链。 逻辑单元中的至少一个包括用于在提供给一个逻辑单元的一组输入上植入逻辑功能的一个或多个查找表和被配置为接收进位信号并产生进位输出信号的算术逻辑电路 形成第一个进位链的一部分。 在一个实施例中，逻辑单元还包括第一输出寄存器和第二输出寄存器，并且逻辑单元产生的输出集合在第一输出寄存器和第二输出寄存器之间被分区。 在另一实施例中，寄存器之一的输出通过寄存器反馈连接被提供作为单元的查找表之一的输入。 在另一个实施例中，提供给第一和第二查找表的输入组是不同的，通过使每个单元能够在两组不同的输入集上执行逻辑功能，能够实现更高程度的逻辑效率或“打包”，如 反对只有同一组投入。 最后，在另一个实施例中，算术逻辑电路能够产生两个SUM输出信号。

公开(公告)号：US06429681B1

公开(公告)日：2002-08-06

申请号：US09781056

申请日：2001-02-09

Applicant: Michael D. Hutton

Inventor： Michael D. Hutton

IPC: H03K19177

CPC classification number: H03K19/17736

Abstract: A programmable logic device has registers (“re-timing registers”) associated with interconnection conductors. The re-timing registers are in addition to registers that are conventionally associated with other device elements such as logic and memory cells. Programmable links enable optional data paths through the re-timing registers between disconnected segments of interconnection conductors. Re-timing techniques for optimization of circuit designs seeking to minimize the longest register-to-register path can include positioning of re-timing registers on interconnection conductors. Long interconnection conductors can be used in data paths between device elements with only short segments of interconnection conductors contributing to critical path lengths.

Abstract translation: 可编程逻辑器件具有与互连导体相关联的寄存器（“重新定时寄存器”）。 重新定时寄存器除了通常与诸如逻辑和存储器单元之类的其它器件元件相关联的寄存器之外。 可编程链路通过互连导体的断开部分之间的重新定时寄存器实现可选数据路径。 用于优化寻求最小化寄存器到寄存器最长路径的电路设计的重新定时技术可以包括在互连导体上定位重新定时寄存器。 长互连导体可用于器件元件之间的数据路径，只有短的互连导体段有助于关键路径长度。

公开(公告)号：US08601424B1

公开(公告)日：2013-12-03

申请号：US12893904

申请日：2010-09-29

Applicant: Michael D. Hutton ,  Gregg William Baeckler ,  Jinyong Yuan ,  Chris Wysocki ,  Pouyan Djahani

Inventor： Michael D. Hutton ,  Gregg William Baeckler ,  Jinyong Yuan ,  Chris Wysocki ,  Pouyan Djahani

IPC: G06F17/50

CPC classification number: H03K19/173 ,  H03K19/1736 ,  H03K19/17728

Abstract: A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.