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    Methods and apparatus for control and configuration of programmable logic devices
    1.
    发明授权
    Methods and apparatus for control and configuration of programmable logic devices 失效
    用于控制和配置可编程逻辑器件的方法和装置

    公开(公告)号：US07696781B1

    公开(公告)日：2010-04-13

    申请号：US12291923

    申请日：2008-11-14

    申请人： Ali H. Burney ,  Daniel R. Mansur

    发明人： Ali H. Burney ,  Daniel R. Mansur

    IPC分类号： G06F7/38 ,  H03K19/173

    CPC分类号： H03K19/17732

    摘要： Circuitry and methods are provided for control and configuration of a PLD. An embodiment of the invention comprises hard IP circuitry embedded in the PLD. The circuitry may include a gigabit MAC, a hard processor, and a DMA engine. The invention permits a variety of operations, including real-time control and remote programming, without the use of dedicated external circuitry.

    摘要翻译： 提供电路和方法来控制和配置PLD。 本发明的实施例包括嵌入在PLD中的硬IP电路。 电路可以包括千兆MAC，硬处理器和DMA引擎。 本发明允许多种操作，包括实时控制和远程编程，而不使用专用的外部电路。

    Methods and apparatus for control and configuration of programmable logic devices
    2.
    发明授权
    Methods and apparatus for control and configuration of programmable logic devices 失效
    用于控制和配置可编程逻辑器件的方法和装置

    公开(公告)号：US07468613B1

    公开(公告)日：2008-12-23

    申请号：US11893722

    申请日：2007-08-16

    申请人： Ali H. Burney ,  Daniel R. Mansur

    发明人： Ali H. Burney ,  Daniel R. Mansur

    IPC分类号： G06F7/38 ,  H03K19/173

    CPC分类号： H03K19/17732

    摘要： Circuitry and methods are provided for control and configuration of a PLD. An embodiment of the invention comprises hard IP circuitry embedded in the PLD. The circuitry may include a gigabit MAC, a hard processor, and a DMA engine. The invention permits a variety of operations, including real-time control and remote programming, without the use of dedicated external circuitry.

    摘要翻译： 提供电路和方法来控制和配置PLD。 本发明的实施例包括嵌入在PLD中的硬IP电路。 电路可以包括千兆MAC，硬处理器和DMA引擎。 本发明允许多种操作，包括实时控制和远程编程，而不使用专用的外部电路。

    FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC INTEGRATED CIRCUIT FABRIC
    4.
    发明申请
    FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC INTEGRATED CIRCUIT FABRIC 有权
    具有集成应用的现场可编程阵列阵列集成电路布

    公开(公告)号：US20100207659A1

    公开(公告)日：2010-08-19

    申请号：US12767696

    申请日：2010-04-26

    申请人： Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

    发明人： Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

    IPC分类号： H03K19/177 ,  G06F17/50

    CPC分类号： H03K19/17744 ,  H03K19/17732 ,  H03K19/17796

    摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

    摘要翻译： 提供了具有集成专用集成电路（“ASIC”）结构的现场可编程门阵列（“FPGA”）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由“自定义区域”和“接口区域”组成。自定义区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成并连接到FPGA的其余部分 电路。 定制区域可以基于结构化ASIC设计。 接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

    Field programmable gate array with integrated application specific integrated circuit fabric
    5.
    发明授权
    Field programmable gate array with integrated application specific integrated circuit fabric 有权
    具有集成专用集成电路结构的现场可编程门阵列

    公开(公告)号：US07724032B2

    公开(公告)日：2010-05-25

    申请号：US11894283

    申请日：2007-08-20

    申请人： Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

    发明人： Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17744 ,  H03K19/17732 ,  H03K19/17796

    摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

    摘要翻译： 提供了具有集成专用集成电路（“ASIC”）结构的现场可编程门阵列（“FPGA”）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由“自定义区域”和“接口区域”组成。自定义区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成并连接到FPGA的其余部分 电路。 定制区域可以基于结构化ASIC设计。 接口区域可以允许将ASIC结构并入FPGA的分层组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

    System and apparatus with IC resource interconnect
    7.
    发明授权
    System and apparatus with IC resource interconnect 有权
    具有IC资源互连的系统和设备

    公开(公告)号：US08467218B1

    公开(公告)日：2013-06-18

    申请号：US12966391

    申请日：2010-12-13

    申请人： Sean R. Atsatt ,  Daniel R. Mansur

    发明人： Sean R. Atsatt ,  Daniel R. Mansur

    IPC分类号： G11C5/06

    CPC分类号： G06F13/405

    摘要： Various novel aspects are disclosed by reference to an integrated circuit block that includes programmable regions, and extra-block connection pins or points with adapter circuitry, coupled by an interconnect system. Multiple independent interconnects are disclosed within the interconnect system, as are options for the composition of the programmable regions and their connectivity with the interconnect system. Adapter circuitry is disclosed that includes support for coupling extra-block memory circuits or devices using a variety of modes, protocols, and options. Modular circuit blocks provide flexibility at the interface between programmable region and fixed function circuitry.

    摘要翻译： 通过参考包括可编程区域的集成电路块和通过互连系统耦合的具有适配器电路的多块连接引脚或点来公开各种新颖的方面。 在互连系统中公开了多个独立互连，以及可编程区域的组合及其与互连系统的连接性的选择。 公开了适配器电路，其包括使用各种模式，协议和选项来耦合额外块存储器电路或设备的支持。 模块化电路块在可编程区域和固定功能电路之间的接口处提供灵活性。

    FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC INTEGRATED CIRCUIT FABRIC
    8.
    发明申请
    FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC INTEGRATED CIRCUIT FABRIC 审中-公开
    具有集成应用的现场可编程阵列特殊集成电路布

    公开(公告)号：US20130009666A1

    公开(公告)日：2013-01-10

    申请号：US13613925

    申请日：2012-09-13

    申请人： Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

    发明人： Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17744 ,  H03K19/17732 ,  H03K19/17796

    摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

    摘要翻译： 提供具有集成专用集成电路（ASIC）结构的现场可编程门阵列（FPGA）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由自定义区域和接口区域组成。 定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。 定制区域可以基于结构化ASIC设计。 接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

    Field programmable gate array with integrated application specific integrated circuit fabric
    9.
    发明授权
    Field programmable gate array with integrated application specific integrated circuit fabric 有权
    具有集成专用集成电路结构的现场可编程门阵列

    公开(公告)号：US08314636B2

    公开(公告)日：2012-11-20

    申请号：US12767696

    申请日：2010-04-26

    申请人： Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

    发明人： Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17744 ,  H03K19/17732 ,  H03K19/17796

    摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

    摘要翻译： 提供具有集成专用集成电路（ASIC）结构的现场可编程门阵列（FPGA）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由自定义区域和接口区域组成。 定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。 定制区域可以基于结构化ASIC设计。 接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

    Field programmable gate array with integrated application specific integrated circuit fabric
    10.
    发明申请
    Field programmable gate array with integrated application specific integrated circuit fabric 有权
    具有集成专用集成电路结构的现场可编程门阵列

    公开(公告)号：US20090051387A1

    公开(公告)日：2009-02-26

    申请号：US11894283

    申请日：2007-08-20

    申请人： Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

    发明人： Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17744 ,  H03K19/17732 ,  H03K19/17796

    摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

    摘要翻译： 提供了具有集成专用集成电路（“ASIC”）结构的现场可编程门阵列（“FPGA”）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由“自定义区域”和“接口区域”组成。 定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。 定制区域可以基于结构化ASIC设计。 接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。