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    SOLID STATE TRANSDUCER DEVICES WITH SEPARATELY CONTROLLED REGIONS, AND ASSOCIATED SYSTEMS AND METHODS
    1.
    发明申请
    SOLID STATE TRANSDUCER DEVICES WITH SEPARATELY CONTROLLED REGIONS, AND ASSOCIATED SYSTEMS AND METHODS 有权

    公开(公告)号：US20250169262A1

    公开(公告)日：2025-05-22

    申请号：US19030871

    申请日：2025-01-17

    Applicant: Micron Technology, Inc.

    Inventor： Robert R. Rhodehouse

    IPC: H10H29/14 ,  H10H20/00 ,  H10H20/01 ,  H10H20/811 ,  H10H20/824 ,  H10H20/831

    Abstract: Solid state transducer devices with independently controlled regions, and associated systems and methods are disclosed. A solid state transducer device in accordance with a particular embodiment includes a transducer structure having a first semiconductor material, a second semiconductor material and an active region between the first and second semiconductor materials, the active region including a continuous portion having a first region and a second region. A first contact is electrically connected to the first semiconductor material to direct a first electrical input to the first region along a first path, and a second contact electrically spaced apart from the first contact and connected to the first semiconductor material to direct a second electrical input to the second region along a second path different than the first path. A third electrical contact is electrically connected to the second semiconductor material.

    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    3.
    发明申请
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20250166704A1

    公开(公告)日：2025-05-22

    申请号：US19027291

    申请日：2025-01-17

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Collin Howder ,  Jordan D. Greenlee

    IPC: G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. The lower portion comprises an upper second tier comprising insulative material. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the upper portion to the lower portion. Horizontally-elongated lines are formed in the upper second tier longitudinally-along opposing lateral edges of the memory-block regions. Material of the lines is of different composition from that of the insulative material in the upper second tier that is laterally-between the lines. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and that extend through the upper portion to the lower portion. Other embodiments, including structure independent of method, are disclosed.

    MANAGEMENT OF DYNAMIC READ VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM
    4.
    发明申请
    MANAGEMENT OF DYNAMIC READ VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM 有权

    公开(公告)号：US20250166696A1

    公开(公告)日：2025-05-22

    申请号：US19030522

    申请日：2025-01-17

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Zhenming Zhou

    IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/4076

    Abstract: A memory subsystem receives a first read command and a second read command. Responsive to determining that the first read command originated from a host system, the memory subsystem selects a reverse read trim setting. Responsive to determining that the second read command did not originate from the host system, the memory subsystem selects a forward read trim setting. The memory subsystem executes the first read command using the reverse read trim setting. The memory subsystem executes the second read command using the forward read trim setting.

    SEPARATE BRANCH TARGET BUFFERS FOR DIFFERENT LEVELS OF CALLS
    6.
    发明申请
    SEPARATE BRANCH TARGET BUFFERS FOR DIFFERENT LEVELS OF CALLS 有权

    公开(公告)号：US20250165256A1

    公开(公告)日：2025-05-22

    申请号：US19023081

    申请日：2025-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Steven Jeffrey Wallach

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

    Abstract: A computing device (e.g., a processor) having a plurality of branch target buffers. A first branch target buffer in the plurality of branch target buffers is used in execution of a set of instructions containing a call to a subroutine. In response to the call to the subroutine, a second branch target buffer is allocated from the plurality of branch target buffers for execution of instructions in the subroutine. The second branch target buffer is cleared before the execution of the instructions in the subroutine. The execution of the instructions in the subroutine is restricted to access the second branch target buffer and blocked from accessing branch target buffers other than the second branch target buffer.

    MEMORY DEVICE WITH A SPLIT PILLAR ARCHITECTURE
    7.
    发明申请
    MEMORY DEVICE WITH A SPLIT PILLAR ARCHITECTURE 有权

    公开(公告)号：US20250159910A1

    公开(公告)日：2025-05-15

    申请号：US18952568

    申请日：2024-11-19

    Applicant: Micron Technology, Inc.

    Inventor： Lorenzo Fratin ,  Fabio Pellizzer ,  Paolo Fantini

    IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

    Abstract: Methods, systems, and devices for memory device with a split pillar architecture are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars and cell material may be divided to form a first and second storage components and first and second pillars.

    SEMICONDUCTOR DEVICES COMPRISING CARBON-DOPED SILICON NITRIDE
    10.
    发明申请
    SEMICONDUCTOR DEVICES COMPRISING CARBON-DOPED SILICON NITRIDE 有权

    公开(公告)号：US20250159877A1

    公开(公告)日：2025-05-15

    申请号：US19022523

    申请日：2025-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

    IPC: H10B41/30 ,  H01L21/768 ,  H10B41/20 ,  H10B41/47 ,  H10B41/50 ,  H10B43/50

    Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

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