公开(公告)号：US20250072079A1

公开(公告)日：2025-02-27

申请号：US18947497

申请日：2024-11-14

Applicant: Micron Technology, Inc.

Inventor： Thomas M. Graettinger

IPC: H01L29/66 ,  H01L27/06 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

Abstract: The present disclosure includes methods for replacement gate formation in memory, and apparatuses and systems including memory formed accordingly. An embodiment includes forming a first oxide material in an opening through alternating layers of a second oxide material and a nitride material. An array of openings can be formed through the first oxide material formed in the opening. The layers of the nitride material can be removed. A metal material can be formed in voids resulting from the removal of the layers of the nitride material.

公开(公告)号：US20250069683A1

公开(公告)日：2025-02-27

申请号：US18782624

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Luyen Vu ,  Alex Sheng-Huang Lee ,  Wei Lic Chew

IPC: G11C29/00

Abstract: A memory device includes a memory array includes memory cells grouped into one or more address ranges. Control logic is coupled to the memory array and configured to detect one or more errors associated with one or more stored data items corresponding to a first address range of one or more address ranges. The control logic can determine that a number of the one or more stored data items exceeds a number of redundant memory locations for the first address space. Control logic can remap an association of a first memory address of at least one of the stored data items from a first address within the first address space to a second address in a second address range, where the second address range includes one or more available redundant memory locations.

公开(公告)号：US20250069675A1

公开(公告)日：2025-02-27

申请号：US18774642

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： Daniel Zhang ,  Yu-Chung Lien ,  Peng Zhang ,  Murong Lang ,  Zhenming Zhou

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/32

Abstract: The disclosure configures a memory sub-system controller to use prior read verify operations to selectively apply enhancements to read window budgets (RWB). The controller receives a request to perform a memory operation on data stored in an individual memory component of a set of memory components. The controller accesses RWB tracking information associated with the individual memory component and determines that the tracking information associated with the individual memory component indicates a need for enhancing a RWB associated with the memory operation. The controller applies one or more enhancement processes to the individual memory component in response to determining that the tracking information associated with the individual memory component indicates the need for enhancing the RWB associated with the memory operation.

公开(公告)号：US20250069638A1

公开(公告)日：2025-02-27

申请号：US18944400

申请日：2024-11-12

Applicant: Micron Technology, Inc.

Inventor： John E. Riley ,  Joo-Sang Lee ,  Scott E. Smith

IPC: G11C11/406 ,  G11C11/4074

Abstract: Methods, systems, and devices for adjusting a refresh rate during a self-refresh state are described. A memory system may enter a self-refresh state and execute a first set of refresh operations on a set of rows of memory cells at the memory system according to a first rate. The memory system may determine, based on executing the first set of refresh operations, that a counter associated with the set of refresh operations satisfies a threshold for a second time while the memory system is in the self-refresh state. In response to the counter satisfying the threshold for the second time, a flip-flop circuit at the memory system may modify an output of the flip-flop circuit and the memory system may decrease the rate for executing the refresh operations to a second rate based on the modified output of the flip-flop circuit.

公开(公告)号：US20250068802A1

公开(公告)日：2025-02-27

申请号：US18787773

申请日：2024-07-29

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Shashank Bangalore Lakshman ,  Pavana Prakash ,  Febin Sunny

IPC: G06F30/27 ,  G06F30/15

Abstract: Systems, methods, and apparatuses related to a network for behavior modeling are described. A network can include surveillance devices that are each configured to collect pedestrian behavior data corresponding to a geographic region and output local pedestrian behavior model updates to a municipal communication node for the geographic region. The municipal communication node is configured to receive the local pedestrian behavior model updates and output the local pedestrian behavior model updates to a global pedestrian behavior model to aggregate the local pedestrian behavior model updates. A processing device is coupled to the municipal communication node and is configured to output the global pedestrian behavior model to the municipal communication node. The municipal communication node is configured to output the global pedestrian behavior model to an automatic driver assistance system (ADAS) in a vehicle within the geographic region, wherein the vehicle operates based on the global pedestrian behavior model.

公开(公告)号：US20250068334A1

公开(公告)日：2025-02-27

申请号：US18948308

申请日：2024-11-14

Applicant: Micron Technology, Inc.

Inventor： Srinivasa Anuradha Bulusu ,  Akshaya Venkatakrishnan ,  Alaa Ali

IPC: G06F3/06

Abstract: Methods of reusing and/or repurposing microelectronic devices are disclosed. A method may include enabling a reuse mode on a memory device responsive to the memory device being fit for a secondary application. The method may further include reconfiguring the memory device responsive to enabling the reuse mode. Associated systems are also disclosed.

公开(公告)号：US20250068231A1

公开(公告)日：2025-02-27

申请号：US18945044

申请日：2024-11-12

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik

IPC: G06F1/3296 ,  G06F1/324

Abstract: An example method for voltage frequency scaling based on error rate can include performing a plurality of monitoring operations on a system on chip (SoC) at a respective plurality of voltage values (and/or plurality of frequency values and/or temperature values). The example method can include causing error rate data gathered from each of the plurality of monitoring operations to be entered into a database, wherein the entered error rate data is associated with the plurality of voltage values. The entered data is associated with the respective plurality of voltage value. The example method can include generating a plot using the error rate date in the database. The example method can include determining a particular voltage value greater than each of the plurality of voltage values based on the plot and a particular error rate associated with the particular voltage value.

公开(公告)号：US12238015B2

公开(公告)日：2025-02-25

申请号：US17866318

申请日：2022-07-15

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: H04L49/00 ,  H04L49/103 ,  H04L49/90 ,  H04L67/1097

Abstract: A memory sub-system connectable to a microprocessor to provide network storage services. The memory sub-system has a random-access memory configured with: first queues for the microprocessor and a network interface; second queues for the microprocessor and a processing device; and third queues for the processing device and a storage device. The processing device is configured to: generate first control messages and first data messages from packets received by the network interface; place the first control messages into the first queues for the microprocessor; and place the first data messages into the third queues for the storage device. The microprocessor processes the first control messages to implement security and administrative functions and place second control messages in the second queues. The storage device is configured to retrieve the first data messages from the third queues and second control messages from the second queues for processing.

公开(公告)号：US12237301B2

公开(公告)日：2025-02-25

申请号：US17750225

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package including a package substrate with an upper surface, a controller, and a die stack. The controller and the die stack are at the upper surface. The die stack includes a shingled sub-stack of semiconductor dies, a reverse-shingled sub-stack of semiconductor dies, and a bridging chip. The bridging chip is bonded between the shingled sub-stack and the reverse-shingled sub-stack, and has an internal trace. A first wire segment is bonded between the controller and a first end of the bridging chip, and a second wire segment is bonded between a second end of the bridging chip and each semiconductor die of the shingled sub-stack. The internal trace electrically couples the first and second wire segments. Additionally, a third wire segment is bonded between the controller and each semiconductor die of the reverse-shingled sub-stack.

公开(公告)号：US12237259B2

公开(公告)日：2025-02-25

申请号：US17443531

申请日：2021-07-27

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Harsh Narendrakumar Jain ,  Naveen Kaushik ,  Adam L. Olson ,  Richard J. Hill ,  Lars P. Heineck

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H10B41/35 ,  H10B43/35

Abstract: An electronic device comprising multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Methods of forming an electronic device and related systems are also disclosed.