公开(公告)号：US5084838A

公开(公告)日：1992-01-28

申请号：US391783

申请日：1989-08-09

申请人： Takeshi Kajimoto ,  Mitsuteru Kobayashi

发明人： Takeshi Kajimoto ,  Mitsuteru Kobayashi

IPC分类号： G06F11/20 ,  G11C8/12 ,  G11C29/00

CPC分类号： G11C29/006 ,  G11C8/12

摘要： A plurality of unit integrated circuits mounted on a large-scale integrated circuit device, for example, a wafer scale memory, are each provided with a bypass circuit which selectively shorts input and output nodes in the corresponding unit integrated circuit. By selectively bringing the bypass circuit into a transfer state, it is possible to effectively couple together all unit integrated circuits which are judged to be normal among a plurality of unit integrated circuits disposed along one row, for example. Improved redundancy arrangements are also provided, including first and second redundant elements for the unit integrated circuits, to effectively utilize the normal elements in the unit integrated circuits. Further, an improved arrangement for hierarchically connecting together the outputs of all the unit circuit blocks is provided which reduces the signal line load for the memory device.

摘要翻译： 安装在大规模集成电路装置（例如，晶片刻度存储器）上的多个单元集成电路各自设置有旁路电路，其选择性地缩短相应的单元集成电路中的输入和输出节点。 通过选择性地使旁路电路进入传送状态，例如可以将沿着一行布置的多个单元集成电路中被判断为正常的所有单元集成电路有效地耦合在一起。 还提供了改进的冗余布置，包括用于单元集成电路的第一和第二冗余元件，以有效地利用单元集成电路中的正常元件。 此外，提供了用于将所有单元电路块的输出分层连接在一起的改进布置，其减少了存储器件的信号线负载。

公开(公告)号：US5463249A

公开(公告)日：1995-10-31

申请号：US982169

申请日：1992-11-24

申请人： Yutaka Shinbo ,  Takeshi Kajimoto ,  Mitsuteru Kobayashi ,  Katsuyuki Sato

发明人： Yutaka Shinbo ,  Takeshi Kajimoto ,  Mitsuteru Kobayashi ,  Katsuyuki Sato

IPC分类号： H01L21/822 ,  G11C5/00 ,  H01L23/538 ,  H01L25/18 ,  H01L27/04 ,  H01L23/48 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

CPC分类号： H01L25/18 ,  H01L23/5385 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165

摘要： In an electronic circuit system unit having a semiconductor integrated circuit unit on a wafer scale, a semiconductor wafer (a semiconductor integrated circuit unit on a wafer scale) and a print wiring substrate are laid to overlap each other and semiconductor pellets are mounted on the print wiring substrate in the overlapping area of the print wiring substrate and the semiconductor wafer. In said electronic circuit system unit, an area being a part of the periphery of the semiconductor wafer is protruded from the periphery of the print wiring substrate being placed to overlap the semiconductor wafer, and the semiconductor wafer and the print wiring substrate are electrically connected to each other in an area being a part of the protruded part through wires.

摘要翻译： 在具有晶片尺寸上的半导体集成电路单元的电子电路系统单元中，放置半导体晶片（晶片上的半导体集成电路单元）和印刷布线基板以彼此重叠，将半导体芯片安装在打印机 布线基板在印刷布线基板和半导体晶片的重叠区域中。 在所述电子电路系统单元中，作为半导体晶片的周边的一部分的区域从被布置为与半导体晶片重叠的印刷布线基板的周边突出，并且半导体晶片和印刷布线基板电连接到 在通过导线的突出部分的一个区域中彼此相对。

公开(公告)号：US5420824A

公开(公告)日：1995-05-30

申请号：US180510

申请日：1994-01-12

申请人： Takeshi Kajimoto ,  Mitsuteru Kobayashi ,  Katsuyuki Sato ,  Yutaka Shimbo

发明人： Takeshi Kajimoto ,  Mitsuteru Kobayashi ,  Katsuyuki Sato ,  Yutaka Shimbo

IPC分类号： G11C29/00 ,  G11C11/401 ,  G11C11/408 ,  G11C11/409 ,  G11C11/411 ,  G11C29/04 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  G11C13/00

CPC分类号： G11C29/70 ,  G11C29/76

摘要： In LSI circuit devices having a plurality of subchips packaged therein and having specific functions, capacitance cutting buffer circuits are employed in conjunction with respective terminals of the subchips, and a driver is disposed at respective points where relatively long wiring lines are respectively sub-divided into a corresponding plurality of lines. As a result, signal transmission delay can be significantly reduced. The terminals of the subchips are also provided with a probing pad to test the operations of the subchips independently of one another. The subchips employ circuit blocks which are to operate simultaneously and in conjunction with the wirings of the subchips, power supply lines are disposed correspondingly to the distributively arranged circuit blocks. Bus lines also controllably transmit addresses as well as data signals in a time sharing manner. Furthermore, each of the subchips has a fault test circuit. The subchips which have a DC fault is electrically isolated thereby allowing the remainder of the subchip to be usable. In the fault relieving technique employed, a combination of memory locations wherein no fault exists is selected for use, thereby allowing the construction of an LSI even with subchips which correspond to faulty bit addresses. The fault relieving technique employed uses an address converting circuit for faulty addresses, this operation being performed automatically within the chip system.

摘要翻译： 在具有封装在其中并具有特定功能的多个子芯片的LSI电路装置中，与子芯片的各个端子一起使用电容切割缓冲电路，并且驱动器设置在相对较长的布线分别分为 相应的多行。 结果，可以显着地减少信号传输延迟。 子芯片的端子还设有探测板，以独立于彼此测试子芯片的操作。 子芯片采用同时操作并与子芯片的布线一起工作的电路块，电源线相对于分布式布置的电路块设置。 总线也可以以时间分配方式可控地发送地址以及数据信号。 此外，每个子芯片具有故障测试电路。 具有DC故障的子芯片被电隔离，从而允许子芯片的其余部分可用。 在采用的故障消除技术中，选择存在无故障的存储器位置的组合，从而即使使用与故障位地址相对应的子芯片也可以构造LSI。 所采用的故障消除技术使用地址转换电路用于故障地址，该操作在芯片系统内自动执行。