公开(公告)号：US5537538A

公开(公告)日：1996-07-16

申请号：US166969

申请日：1993-12-15

申请人： Joseph P. Bratt ,  John Brennan ,  Peter Y. Hsu ,  Chandra S. Joshi ,  William A. Huffman ,  Monica R. Nofal ,  Paul Rodman ,  Joseph T. Scanlon ,  Man K. Tang

发明人： Joseph P. Bratt ,  John Brennan ,  Peter Y. Hsu ,  Chandra S. Joshi ,  William A. Huffman ,  Monica R. Nofal ,  Paul Rodman ,  Joseph T. Scanlon ,  Man K. Tang

IPC分类号： D06M13/46 ,  C11D1/04 ,  C11D1/62 ,  C11D1/645 ,  C11D1/65 ,  C11D1/72 ,  C11D1/835 ,  C11D3/00 ,  D06M20060101 ,  D06M13/02 ,  D06M13/184 ,  D06M13/188 ,  D06M13/322 ,  D06M13/463 ,  G06F9/38 ,  G06F11/36 ,  G06F11/34 ,  G06F9/30

CPC分类号： G06F11/3664 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885

摘要： A processor system that is switchable between a normal mode of operation without precise floating point exceptions and a debug mode of operation with precise floating point exceptions. The processor system includes a dispatch for dispatching integer and floating point instructions, an integer unit having a multi-stage integer pipeline for executing the integer instructions, and a floating point unit having a multi-stage floating point pipeline for executing the floating point instructions. The system begins operation in the normal mode, and upon receipt of an instruction to "switch to debug mode," the processor switches to the debug mode of operation with precise exceptions. In the debug mode, once a floating point instruction has been dispatched, all other instructions are prevented from being committed until the system determines whether the floating point instruction generates an exception. Thus, permitting the system to signal precise exceptions when not in the normal mode.

摘要翻译： 处理器系统，可在正常操作模式之间切换，无需精确的浮点异常，以及具有精确浮点异常的调试操作模式。 处理器系统包括调度整数和浮点指令的调度，具有用于执行整数指令的多级整数流水线的整数单元，以及具有用于执行浮点指令的多级浮点流水线的浮点单元。 系统在正常模式下开始运行，并且在接收到“切换到调试模式”的指令时，处理器切换到调试操作模式，具有精确的例外。 在调试模式下，一旦调度了浮点指令，就会阻止所有其他指令被提交，直到系统确定浮点指令是否产生异常。 因此，允许系统在不处于正常模式时发出精确异常。

公开(公告)号：US5510934A

公开(公告)日：1996-04-23

申请号：US168832

申请日：1993-12-15

申请人： John Brennan ,  Peter Y. Hsu ,  William A. Huffman ,  Paul Rodman ,  Joseph T. Scanlon ,  Man K. Tang ,  Steve J. Ciavaglia

发明人： John Brennan ,  Peter Y. Hsu ,  William A. Huffman ,  Paul Rodman ,  Joseph T. Scanlon ,  Man K. Tang ,  Steve J. Ciavaglia

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0897 ,  G06F12/0831 ,  G06F12/0851

摘要： A split level cache memory system for a data processor includes a single chip integer unit, an army processor such as a floating point unit, an external main memory and a split level cache. The split level cache includes an on-chip, fast local cache with low latency for use by the integer unit for loads and stores of integer and address data and an off-chip, pipelined global cache for storing arrays of data such as floating point data for use by the array processor and integer and address data for refilling the local cache. Coherence between the local cache and global cache is maintained by writing through to the global cache during integer stores. Local cache words are invalidated when data is written to the global cache during an army processor store.

摘要翻译： 用于数据处理器的分级高速缓冲存储器系统包括单个芯片整数单元，诸如浮点单元的陆军处理器，外部主存储器和分割级高速缓存。 分级高速缓存包括片上快速本地高速缓存，具有低延迟，用于整数单元用于整数和地址数据的加载和存储，以及用于存储诸如浮点数据的数据阵列的片外流水线全局高速缓存 供数组处理器使用，整数和地址数据用于重新填充本地缓存。 通过在整数存储期间写入全局缓存来维护本地缓存和全局缓存之间的一致性。 在陆军处理器存储期间将数据写入全局缓存时，本地缓存字无效。

公开(公告)号：US5572704A

公开(公告)日：1996-11-05

申请号：US167005

申请日：1993-12-15

申请人： Joseph P. Bratt ,  John Brennan ,  Peter Y. Hsu ,  William A. Huffman ,  Joseph T. Scanlon ,  Steve Ciavagia

发明人： Joseph P. Bratt ,  John Brennan ,  Peter Y. Hsu ,  William A. Huffman ,  Joseph T. Scanlon ,  Steve Ciavagia

IPC分类号： G06F12/08 ,  G06F12/16

CPC分类号： G06F12/0811

摘要： A method for preventing data loss and deadlock in a multi-processor computer system wherein at least one processor in the computer system includes a split-level cache. The split-level cache has a byte-writable first-level and a word-writable second level. The method monitors the second level cache to determine if a forced atomic (FA) instruction is in a second level cache pipeline. If an FA instruction is determined to be in the second level cache pipeline, then interventions to the second level cache are delayed until the FA instruction exits the second level cache pipeline. In this manner data written by operation of cache memory access instruction that cause the interventions is not destroyed by the execution of the FA instruction, thereby preventing data loss. The method also monitors the second level cache pipeline to determine if a possible miss (PM) instruction is in the second level cache pipeline. If a PM instruction is determined to be in the second level cache pipeline, the FA instructions are prevented from entering the second level cache pipeline such that execution of interventions to the second level cache is not prevented when an instruction in the second level cache may be detained to process an intervention in its behalf, thereby preventing deadlock between processing units of the computer system.

摘要翻译： 一种用于在多处理器计算机系统中防止数据丢失和死锁的方法，其中所述计算机系统中的至少一个处理器包括分级高速缓存。 分级缓存具有可写字节的第一级和可写字的第二级。 该方法监视第二级高速缓存以确定强制原子（FA）指令是否在二级高速缓存流水线中。 如果FA指令被确定在第二级高速缓存流水线中，则延迟到第二级高速缓存的干预，直到FA指令退出第二级高速缓存流水线。 以这种方式，通过执行FA指令不会破坏导致干预的高速缓冲存储器访问指令的操作所写入的数据，从而防止数据丢失。 该方法还监视第二级高速缓存流水线以确定可能的未命中（PM）指令是否在第二级高速缓存流水线中。 如果确定PM指令处于第二级高速缓存流水线中，则FA指令被阻止进入第二级高速缓存流水线，使得当第二级高速缓存中的指令可能为 被拘留以代表其进行干预，从而防止计算机系统的处理单元之间的僵局。

公开(公告)号：US5632025A

公开(公告)日：1997-05-20

申请号：US696788

申请日：1996-08-14

申请人： Joseph P. Bratt ,  John Brennan ,  Peter Y. T. Hsu ,  William A. Huffman ,  Joseph T. Scanlon ,  Steve Ciavaglia

发明人： Joseph P. Bratt ,  John Brennan ,  Peter Y. T. Hsu ,  William A. Huffman ,  Joseph T. Scanlon ,  Steve Ciavaglia

IPC分类号： G06F12/08 ,  G06F12/14

CPC分类号： G06F12/0811

摘要： A method for preventing deadlock due to the need for data exclusivity when performing forced atomic instructions in a multi-level cache in a multi-processor system. The system determines whether an aligned multi-byte word in which the data of a forced atomic instruction, such as an integer store operation, is exclusive in a first level cache. If so, the forced atomic instruction is allowed to enter a second level cache pipeline. If not, the forced atomic instruction is prevented from entering the second level cache pipeline and a cache miss and fill operation is initiated to cause the aligned word to be exclusive in the first level cache.

摘要翻译： 一种用于在多处理器系统中的多级缓存中执行强制原子指令时由于需要数据排他性而防止死锁的方法。 系统确定其中诸如整数存储操作的强制原子指令的数据在第一级高速缓存中是否排他的对齐的多字节字。 如果是这样，则强制原子指令被允许进入第二级高速缓存流水线。 如果不是，则强制原子指令被阻止进入第二级高速缓存流水线并且启动高速缓存未命中和填充操作以使对齐的字在第一级高速缓存中是排他的。

公开(公告)号：US07500068B1

公开(公告)日：2009-03-03

申请号：US11426538

申请日：2006-06-26

申请人： Daniel E. Lenoski ,  Jeffrey S. Kuskin ,  William A. Huffman ,  Michael S. Woodacre

发明人： Daniel E. Lenoski ,  Jeffrey S. Kuskin ,  William A. Huffman ,  Michael S. Woodacre

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F15/167

CPC分类号： G06F12/0817 ,  G06F12/0813

摘要： A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors and a processor memory. Shared access to data in the processor memory of each processor coherence domain is provided only to elements of the multiprocessor system within the processor coherence domain. Non-shared access to data in the processor memory of each processor coherence domain is provided to elements of the multiprocessor system within and outside of the processor coherence domain.

摘要翻译： 用于管理多处理器系统中的存储器的方法和系统包括在多处理器系统的系统相干域内定义多个处理器相干域。 处理器相干域各自包括多个处理器和处理器存储器。 每个处理器一致性域的处理器存储器中的数据的共享访问仅提供给处理器相干域内的多处理器系统的元件。 每个处理器相干域的处理器存储器中的数据的非共享访问被提供给处理器相干域内部和外部的多处理器系统的元件。

公开(公告)号：US06816947B1

公开(公告)日：2004-11-09

申请号：US09909705

申请日：2001-07-20

申请人： William A. Huffman

发明人： William A. Huffman

IPC分类号： G06F1200

CPC分类号： G06F13/1642 ,  G06F12/0813 ,  G06F2212/2542

摘要： A memory access arbitration scheme is provided where transactions to a Shared memory are stored in an arbitration queue. Prior to arbitration, the transactions are compared against the contents of cache memory, to determine which transactions will hit in cache, which will miss and which will be victims. Also prior to arbitration, the entries in the arbitration queue are grouped according to a transaction parameter, such as DRAM bank, Write to Bank, Read to Bank, etc. Arbitration is the performed among those groups which are ready for service. From the group winning arbitration, the oldest transaction is selected for servicing. Preferably, a collapsible queuing structure and method is used, such that once a transaction is serviced, higher order entries ripple down in the queue to make room for new entries while maintaining an oldest to newest relationship among the queue entries.

摘要翻译： 提供存储器访问仲裁方案，其中向共享存储器的事务存储在仲裁队列中。 在仲裁之前，将事务与高速缓存的内容进行比较，以确定哪些事务将在高速缓存中发生，哪些将丢失，哪些将成为受害者。 另外在仲裁之前，仲裁队列中的条目根据事务参数进行分组，如DRAM银行，写入银行，读银行等。仲裁是在准备服务的组之间进行的。 从获胜的仲裁中，选择最旧的交易进行维修。 优选地，使用可折叠排队结构和方法，使得一旦事务被服务，高阶条目在队列中下降以便为新条目腾出空间，同时保持队列条目中最旧到最新的关系。

公开(公告)号：US06795900B1

公开(公告)日：2004-09-21

申请号：US09910363

申请日：2001-07-20

申请人： Steven C. Miller ,  Jeffrey S. Kuskin ,  William A. Huffman ,  Gregory M. Thorson

发明人： Steven C. Miller ,  Jeffrey S. Kuskin ,  William A. Huffman ,  Gregory M. Thorson

IPC分类号： G06F1200

CPC分类号： G06F12/0817 ,  G06F2212/2542 ,  G06F2212/621

摘要： A multiprocessor system and method includes a processing sub-system including a plurality of processors in a processor memory system. A network is operable to couple the processing sub-system to an input/output (I/O) sub-system. The I/O sub-system includes a plurality of I/O interfaces each operable to couple a peripheral device to the multiprocessor system. The I/O interfaces each include a local memory operable to store exclusive read-only copies of data from the processor memory system for use by a corresponding peripheral device.

摘要翻译： 多处理器系统和方法包括在处理器存储器系统中包括多个处理器的处理子系统。 网络可操作以将处理子系统耦合到输入/输出（I / O）子系统。 I / O子系统包括多个I / O接口，每个I / O接口可操作以将外围设备耦合到多处理器系统。 I / O接口各自包括本地存储器，其可操作以存储来自处理器存储器系统的数据的专用只读副本以供对应的外围设备使用。

公开(公告)号：US5933650A

公开(公告)日：1999-08-03

申请号：US947649

申请日：1997-10-09

申请人： Timothy J. van Hook ,  Peter Hsu ,  William A. Huffman ,  Henry P. Moreton ,  Earl A. Killian

发明人： Timothy J. van Hook ,  Peter Hsu ,  William A. Huffman ,  Henry P. Moreton ,  Earl A. Killian

IPC分类号： G06F5/00 ,  G06F7/76 ,  G06F9/30 ,  G06F9/315 ,  G06F15/80

CPC分类号： G06F7/76 ,  G06F5/00 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30167 ,  G06F2207/3828

摘要： The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register. Then, a subset of elements are selected from the first register and the second register. The elements from the subset are then replicated into the elements in the third register in a particular order suitable for subsequent SIMD vector processing.

摘要翻译： 本发明提供用于SIMD处理的向量元素的对准和排序。 在用于SIMD处理的向量元素的对齐中，一个向量从存储器单元加载到第一寄存器中，另一个向量从存储器单元加载到第二寄存器中。 第一个向量包含要生成的对齐向量的第一个字节。 然后，确定指定对齐向量的第一个字节的起始字节。 接下来，从第一寄存器提取向量，并且从第一寄存器的第一字节的第一位开始的第二寄存器继续通过第二寄存器中的位。 最后，将所提取的矢量复制到第三寄存器中，使得第三寄存器包含对准用于SIMD处理的多个元素。 在用于SIMD处理的向量元素的排序中，将第一向量从存储器单元加载到第一寄存器中，并且将第二向量从存储器单元加载到第二寄存器中。 然后，从第一寄存器和第二寄存器中选择元件的子集。 然后将来自子集的元素以适合于随后的SIMD向量处理的特定顺序复制到第三寄存器中的元素中。

公开(公告)号：US5586270A

公开(公告)日：1996-12-17

申请号：US129686

申请日：1993-09-30

申请人： Michael J. Rotier ,  William A. Huffman

发明人： Michael J. Rotier ,  William A. Huffman

IPC分类号： G06F13/40 ,  G06F12/08 ,  G06F13/00

CPC分类号： G06F13/4068

摘要： The computer system having a first circuit board with a processor for processing information and a slot for receiving an IC card. The slot includes multiple pins for connection to the IC card. The IC card includes a second processor coupled to a second circuit board, where the processor is contained within outer framing structure. An interface coupled to the circuit board may be coupled to the multiple pins in the slot, such that the second processor in the integrated circuit card is able to control the computer system.

摘要翻译： 该计算机系统具有具有用于处理信息的处理器的第一电路板和用于接收IC卡的插槽。 该插槽包括多个引脚用于连接到IC卡。 IC卡包括耦合到第二电路板的第二处理器，其中处理器被包含在外框架结构内。 耦合到电路板的接口可以耦合到插槽中的多个引脚，使得集成电路卡中的第二处理器能够控制计算机系统。

公开(公告)号：US5493523A

公开(公告)日：1996-02-20

申请号：US167006

申请日：1993-12-15

申请人： William A. Huffman

发明人： William A. Huffman

IPC分类号： G06F7/52 ,  G06F7/535

CPC分类号： G06F7/535 ,  G06F2207/5353

摘要： A mechanism for dividing an integer dividend by an integer divisor to generate an integer quotient operates by aligning the divisor relative to the dividend such that a right-most bit of the divisor is aligned with a bit M of the dividend. The divisor is compared to an integer value whose right-most bits are equal to bits of the dividend which are aligned with bits of the divisor. As a result of this comparison, quotient bits which positionally correspond to the dividend bit M and to bits of the dividend which are located to the left of the dividend bit M are cleared to zero. Also as a result of the comparison, the dividend is divided by the divisor as aligned relative to the dividend to thereby generate values for any uncleared quotient bits.

摘要翻译： 将整数除数除以整数除数以产生整数商的机制通过将除数相对于被除数进行对齐来操作，使得除数的最右边位与被除数的位M对齐。 将除数与其最右位等于与除数位对齐的被除数位的整数值进行比较。 作为该比较的结果，定位对应于除数位M的商位和位于被除数位M左侧的被除数的位被清除为零。 另外作为比较的结果，除数除以除数与被除数对齐，从而生成任何未清除的商数的值。