公开(公告)号：US5537538A

公开(公告)日：1996-07-16

申请号：US166969

申请日：1993-12-15

申请人： Joseph P. Bratt ,  John Brennan ,  Peter Y. Hsu ,  Chandra S. Joshi ,  William A. Huffman ,  Monica R. Nofal ,  Paul Rodman ,  Joseph T. Scanlon ,  Man K. Tang

发明人： Joseph P. Bratt ,  John Brennan ,  Peter Y. Hsu ,  Chandra S. Joshi ,  William A. Huffman ,  Monica R. Nofal ,  Paul Rodman ,  Joseph T. Scanlon ,  Man K. Tang

IPC分类号： D06M13/46 ,  C11D1/04 ,  C11D1/62 ,  C11D1/645 ,  C11D1/65 ,  C11D1/72 ,  C11D1/835 ,  C11D3/00 ,  D06M20060101 ,  D06M13/02 ,  D06M13/184 ,  D06M13/188 ,  D06M13/322 ,  D06M13/463 ,  G06F9/38 ,  G06F11/36 ,  G06F11/34 ,  G06F9/30

CPC分类号： G06F11/3664 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885

摘要： A processor system that is switchable between a normal mode of operation without precise floating point exceptions and a debug mode of operation with precise floating point exceptions. The processor system includes a dispatch for dispatching integer and floating point instructions, an integer unit having a multi-stage integer pipeline for executing the integer instructions, and a floating point unit having a multi-stage floating point pipeline for executing the floating point instructions. The system begins operation in the normal mode, and upon receipt of an instruction to "switch to debug mode," the processor switches to the debug mode of operation with precise exceptions. In the debug mode, once a floating point instruction has been dispatched, all other instructions are prevented from being committed until the system determines whether the floating point instruction generates an exception. Thus, permitting the system to signal precise exceptions when not in the normal mode.

摘要翻译： 处理器系统，可在正常操作模式之间切换，无需精确的浮点异常，以及具有精确浮点异常的调试操作模式。 处理器系统包括调度整数和浮点指令的调度，具有用于执行整数指令的多级整数流水线的整数单元，以及具有用于执行浮点指令的多级浮点流水线的浮点单元。 系统在正常模式下开始运行，并且在接收到“切换到调试模式”的指令时，处理器切换到调试操作模式，具有精确的例外。 在调试模式下，一旦调度了浮点指令，就会阻止所有其他指令被提交，直到系统确定浮点指令是否产生异常。 因此，允许系统在不处于正常模式时发出精确异常。

公开(公告)号：US5510934A

公开(公告)日：1996-04-23

申请号：US168832

申请日：1993-12-15

申请人： John Brennan ,  Peter Y. Hsu ,  William A. Huffman ,  Paul Rodman ,  Joseph T. Scanlon ,  Man K. Tang ,  Steve J. Ciavaglia

发明人： John Brennan ,  Peter Y. Hsu ,  William A. Huffman ,  Paul Rodman ,  Joseph T. Scanlon ,  Man K. Tang ,  Steve J. Ciavaglia

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0897 ,  G06F12/0831 ,  G06F12/0851

摘要： A split level cache memory system for a data processor includes a single chip integer unit, an army processor such as a floating point unit, an external main memory and a split level cache. The split level cache includes an on-chip, fast local cache with low latency for use by the integer unit for loads and stores of integer and address data and an off-chip, pipelined global cache for storing arrays of data such as floating point data for use by the array processor and integer and address data for refilling the local cache. Coherence between the local cache and global cache is maintained by writing through to the global cache during integer stores. Local cache words are invalidated when data is written to the global cache during an army processor store.

摘要翻译： 用于数据处理器的分级高速缓冲存储器系统包括单个芯片整数单元，诸如浮点单元的陆军处理器，外部主存储器和分割级高速缓存。 分级高速缓存包括片上快速本地高速缓存，具有低延迟，用于整数单元用于整数和地址数据的加载和存储，以及用于存储诸如浮点数据的数据阵列的片外流水线全局高速缓存 供数组处理器使用，整数和地址数据用于重新填充本地缓存。 通过在整数存储期间写入全局缓存来维护本地缓存和全局缓存之间的一致性。 在陆军处理器存储期间将数据写入全局缓存时，本地缓存字无效。

公开(公告)号：US06691221B2

公开(公告)日：2004-02-10

申请号：US09863898

申请日：2001-05-24

申请人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

发明人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

IPC分类号： G06F938

CPC分类号： G06F9/3885 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3844

摘要： A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. The instruction loading circuit loads the L instructions from the second instruction storing circuit into the positions previously occupied by the L instructions dispatched from the first instruction storing circuit. A feedback path is also provided to reload an instruction not previously dispatched.

摘要翻译： 计算系统具有第一和第二指令存储电路，每个指令存储电路存储用于并行输出的N个指令。 耦合到第一指令存储电路的指令调度电路调度存储在第一指令存储电路中的L指令，其中L小于或等于N.一个指令加载电路，耦合到指令调度电路和第一和第二指令 指令存储电路，在从第一指令存储电路发出L指令之后并且从第一指令存储电路调度进一步的指令之前，将来自第二指令存储电路的L指令加载到第一指令存储电路中。 指令加载电路将来自第二指令存储电路的L指令加载到先前由从第一指令存储电路分派的L指令占据的位置。 还提供反馈路径来重新加载先前未发送的指令。

公开(公告)号：US5604909A

公开(公告)日：1997-02-18

申请号：US168744

申请日：1993-12-15

申请人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

发明人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3885 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3844

摘要： A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. A bypass circuit for bypassing the second instruction storing circuit is also provided.

摘要翻译： 计算系统具有第一和第二指令存储电路，每个指令存储电路存储用于并行输出的N个指令。 耦合到第一指令存储电路的指令调度电路调度存储在第一指令存储电路中的L指令，其中L小于或等于N.一个指令加载电路，耦合到指令调度电路和第一和第二指令 指令存储电路，在从第一指令存储电路发出L指令之后并且从第一指令存储电路调度进一步的指令之前，将来自第二指令存储电路的L指令加载到第一指令存储电路中。 还提供了用于绕过第二指令存储电路的旁路电路。

公开(公告)号：US06247124B1

公开(公告)日：2001-06-12

申请号：US09363635

申请日：1999-07-30

申请人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

发明人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

IPC分类号： G06F932

CPC分类号： G06F9/3885 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3844

摘要： A computing system contains an apparatus having an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address. A counter stores an address value used for addressing the instruction memory, and an incrementing circuit increments the address value in the counter for sequentially addressing the lines in the instruction memory during normal sequential operation. A counter loading circuit loads the target address into the counter when the branch prediction entry predicts the branch designated by the branch instruction stored in the instruction memory will be taken when the branch instruction is executed, causing the line containing the target instruction to be fetched and entered into the pipeline immediately after the line containing the branch instruction. An invalidate circuit invalidates any instructions following the branch instruction in the line containing the branch instruction and prior to the target instruction in the line containing the target instruction.

摘要翻译： 计算系统包括具有存储多条指令的多行的指令存储器的装置，以及存储多个分支预测条目的分支存储器，每个分支预测条目包含用于预测分支指定的分支 存储在指令存储器中的指令将在执行分支指令时进行。 每个分支预测条目包括用于指示包含要执行的目标指令的行的目标地址的分支目标字段，如果分支被采用，则指示目标指令位于由分支目标地址指示的行内的目的地字段， 以及指示分支指令在与目标地址对应的行内位于何处的源字段。 计数器存储用于寻址指令存储器的地址值，并且递增电路递增计数器中的地址值，以便在正常顺序操作期间顺序寻址指令存储器中的行。 当分支预测条目预测在执行分支指令时，将采用存储在指令存储器中的分支指令指定的分支，计数器加载电路将目标地址加载到计数器中，导致包含目标指令的行被取出， 在包含分支指令的行后立即进入管道。 无效电路使包含分支指令的行中的分支指令之后的指令和包含目标指令的行中的目标指令之前的任何指令无效。

公开(公告)号：US5954815A

公开(公告)日：1999-09-21

申请号：US781851

申请日：1997-01-10

申请人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

发明人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F9/3885 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3844

摘要： A computing system that contains an apparatus comprising an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address. A counter stores an address value used for addressing the instruction memory, and an incrementing circuit increments the address value in the counter for sequentially addressing the lines in the instruction memory during normal sequential operation. A counter loading circuit loads the target address into the counter when the branch prediction entry predicts the branch designated by the branch instruction stored in the instruction memory will be taken when the branch instruction is executed, causing the line containing the target instruction to be fetched and entered into the pipeline immediately after the line containing the branch instruction. An invalidate circuit invalidates any instructions following the branch instruction in the line containing the branch instruction and prior to the target instruction in the line containing the target instruction.

摘要翻译： 一种计算系统，包括包括存储多条指令的多行的指令存储器和存储多个分支预测条目的分支存储器的装置，每个分支预测条目包含用于预测由a 当执行分支指令时，将采用存储在指令存储器中的分支指令。 每个分支预测条目包括用于指示包含要执行的目标指令的行的目标地址的分支目标字段，如果分支被采用，则指示目标指令位于由分支目标地址指示的行内的目的地字段， 以及指示分支指令在与目标地址对应的行内位于何处的源字段。 计数器存储用于寻址指令存储器的地址值，并且递增电路递增计数器中的地址值，以便在正常顺序操作期间顺序寻址指令存储器中的行。 当分支预测条目预测在执行分支指令时，将采用存储在指令存储器中的分支指令指定的分支，计数器加载电路将目标地址加载到计数器中，导致包含目标指令的行被取出， 在包含分支指令的行后立即进入管道。 无效电路使包含分支指令的行中的分支指令之后的指令和包含目标指令的行中的目标指令之前的任何指令无效。

公开(公告)号：US20070136709A1

公开(公告)日：2007-06-14

申请号：US11608689

申请日：2006-12-08

申请人： Paul Rodman

发明人： Paul Rodman

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： Methods for floorplanning a hierarchical physical design to improve placement and routing are provided and described. In one embodiment, a method of floorplanning a hierarchical physical design includes arranging a plurality of blocks in a top-level of the hierarchical physical design. Each block includes a plurality of linear edges. Additionally, at least one of the blocks is selected. Furthermore, at least one linear edge of the selected block is rasterized. This rasterization includes converting the linear edge to a stepped-shape edge.

摘要翻译： 提供和描述了用于布局规划分层物理设计以改善布局和布线的方法。 在一个实施例中，布局规划分层物理设计的方法包括在分层物理设计的顶层布置多个块。 每个块包括多个线性边缘。 另外，选择至少一个块。 此外，所选块的至少一个线性边缘被光栅化。 该光栅化包括将线性边缘转换成阶梯形边缘。

公开(公告)号：US06757874B1

公开(公告)日：2004-06-29

申请号：US10104786

申请日：2002-03-22

申请人： Peter Dahl ,  Byron Dickinson ,  Margie Levine ,  Paul Rodman

发明人： Peter Dahl ,  Byron Dickinson ,  Margie Levine ,  Paul Rodman

IPC分类号： G06F1750

CPC分类号： G06F17/5068 ,  G06F17/5031

摘要： An abutted-pin hierarchical physical design process is described. The abutted-pin hierarchical physical design provides solutions to the problems of the traditional hierarchical physical design and provides additional advantages and benefits. In particular, the abutted-pin hierarchical physical design does not have channels. Moreover, in the abutted-pin hierarchical physical design, components of the top-level are merged into the block-level so that the top-level netlist is reduced significantly.

摘要翻译： 描述了一种对接的分层物理设计过程。 对接针层级物理设计为传统分层物理设计的问题提供了解决方案，并提供了额外的优点和优点。 特别地，对接针层级物理设计没有通道。 此外，在对接分层物理设计中，顶层的组件被合并到块级，使得顶级网表显着地减少。

公开(公告)号：US20070280262A1

公开(公告)日：2007-12-06

申请号：US11578438

申请日：2005-10-21

申请人： James Larsen ,  Paul Rodman

发明人： James Larsen ,  Paul Rodman

IPC分类号： H04L12/56

CPC分类号： H04W88/04 ,  H04L1/1657 ,  H04W40/246

摘要： A method of operating a communication network having multiple stations, each able to transmit and receive data, so that the network can transmit a message from an originating station to a destination station via at least one opportunistically selected intermediate station. Stations wishing to transmit data transmit probe signals which are responded to by other stations, thereby to identify available stations. When a station has data to send, it transmits probe signals with Request to Send messages, identifying the data to be sent. When a station receives such data for onward transmission, it transmits its own probe signals with a Request to Send message and including identification information relating to the data. The Request to Send messages are received by other stations in the vicinity, so that they serve as an implied acknowledgement of the receipt of the data by the forwarding station without the need for sending explicit confirmation.

摘要翻译： 一种操作具有多个站的通信网络的方法，每个站能够发送和接收数据，使得网络可以经由至少一个机会选择的中间站从发起站向目的地站发送消息。 希望发送数据的站发送由其他站响应的探测信号，从而识别可用站。 当一个站有发送数据时，它发送带有请求发送消息的探测信号，标识要发送的数据。 当站接收到用于向前传输的数据时，它发送具有请求发送消息的其自己的探测信号，并且包括与数据有关的识别信息。 发送请求消息由附近的其他站接收，因此它们作为转发站接收数据的暗示确认，而不需要发送明确的确认。

公开(公告)号：US07114142B1

公开(公告)日：2006-09-26

申请号：US10855667

申请日：2004-05-26

申请人： Russell Segal ,  Paul Rodman

发明人： Russell Segal ,  Paul Rodman

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5031

摘要： Method of optimizing locations of pins for blocks in a hierarchical physical design by using physical design information of a prior hierarchical physical design is provided and described. In one embodiment, a method of determining a plurality of locations of pins for each block of a physical design of a current integrated circuit includes retrieving physical design information from a prior physical design of a prior integrated circuit. The physical design information includes a routing congestion profile. Continuing, a router is provided a plurality of constraints based on the routing congestion profile. Then, the router is used to perform a top-level route for generating locations of pins for each block. Each pin of the block is created at a location where a global route enters the block or a location where a global route exits the block.

摘要翻译： 提供并描述了通过使用先前分层物理设计的物理设计信息来优化分层物理设计中的块的引脚的位置的方法。 在一个实施例中，确定当前集成电路的物理设计的每个块的针的多个位置的方法包括从现有集成电路的先前物理设计中检索物理设计信息。 物理设计信息包括路由拥塞模式。 继续地，基于路由拥塞简档向路由器提供多个约束。 然后，路由器用于执行用于为每个块生成引脚位置的顶级路由。 块的每个引脚在全局路由进入块的位置或全局路由退出块的位置处创建。