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    BINARY CONTROL ARRANGEMENT AND METHOD OF MAKING AND USING THE SAME
    2.
    发明申请
    BINARY CONTROL ARRANGEMENT AND METHOD OF MAKING AND USING THE SAME 有权
    二进制控制装置及其制造和使用方法

    公开(公告)号：US20130314146A1

    公开(公告)日：2013-11-28

    申请号：US13477977

    申请日：2012-05-22

    申请人： Mu-Shan Lin

    发明人： Mu-Shan Lin

    IPC分类号： H03K17/687 ,  H01L21/82

    CPC分类号： H01L27/08 ,  H01L27/0811 ,  H01L27/088

    摘要： The present description relates to a semiconductor device including an array of two or more switching elements and a controller electrically connected to the array of switching elements. At least one switching element of the array of switching elements has a different electrical resistance than at least another switching element of the array of switching elements. The controller is configured to generate and transmit at least one coarse tuning signal and at least one fine tuning signal. The array of switching elements is configured to alter an electrical resistance of the array of switching elements in response to the at least one coarse tuning signal and the at least one fine tuning signal. The present description also includes a method of making a semiconductor device and a method of using a semiconductor device.

    摘要翻译： 本说明书涉及包括两个或多个开关元件的阵列的半导体器件和与开关元件阵列电连接的控制器。 开关元件阵列的至少一个开关元件具有与开关元件阵列的至少另一个开关元件不同的电阻。 控制器被配置为产生和发送至少一个粗调谐信号和至少一个微调信号。 开关元件的阵列被配置为响应于至少一个粗调谐信号和至少一个微调信号而改变开关元件阵列的电阻。 本说明书还包括制造半导体器件的方法和使用半导体器件的方法。

    Binary control arrangement and method of making and using the same
    3.
    发明授权
    Binary control arrangement and method of making and using the same 有权
    二进制控制布置及其使用方法

    公开(公告)号：US08847655B2

    公开(公告)日：2014-09-30

    申请号：US13477977

    申请日：2012-05-22

    申请人： Mu-Shan Lin

    发明人： Mu-Shan Lin

    IPC分类号： H03L5/00

    CPC分类号： H01L27/08 ,  H01L27/0811 ,  H01L27/088

    摘要： The present description relates to a semiconductor device including an array of two or more switching elements and a controller electrically connected to the array of switching elements. At least one switching element of the array of switching elements has a different electrical resistance than at least another switching element of the array of switching elements. The controller is configured to generate and transmit at least one coarse tuning signal and at least one fine tuning signal. The array of switching elements is configured to alter an electrical resistance of the array of switching elements in response to the at least one coarse tuning signal and the at least one fine tuning signal. The present description also includes a method of making a semiconductor device and a method of using a semiconductor device.

    摘要翻译： 本说明书涉及包括两个或多个开关元件的阵列的半导体器件和与开关元件阵列电连接的控制器。 开关元件阵列的至少一个开关元件具有与开关元件阵列的至少另一个开关元件不同的电阻。 控制器被配置为产生和发送至少一个粗调谐信号和至少一个微调信号。 开关元件的阵列被配置为响应于至少一个粗调谐信号和至少一个微调信号而改变开关元件阵列的电阻。 本说明书还包括制造半导体器件的方法和使用半导体器件的方法。

    DUTY CYCLE DETECTION AND CORRECTION CIRCUIT IN AN INTEGRATED CIRCUIT
    5.
    发明申请
    DUTY CYCLE DETECTION AND CORRECTION CIRCUIT IN AN INTEGRATED CIRCUIT 有权
    集成电路中的占空比检测和校正电路

    公开(公告)号：US20140184292A1

    公开(公告)日：2014-07-03

    申请号：US13838406

    申请日：2013-03-15

    申请人： Mu-Shan Lin

    发明人： Mu-Shan Lin

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565 ,  H03K3/017

    摘要： A duty cycle detection and correction circuit includes a clock generator, a clock tree, and a duty cycle correction circuit. The clock generator is configured to generate a first clock signal and a second clock signal, and the first clock signal and the second clock signal have a predetermined phase difference. The clock tree is configured to receive the first clock signal and the second clock signal, to generate a first output clock signal based on the first clock signal and the set of control signals, and to generate a second output clock signal based on the second clock signal and the set of control signals. The duty cycle correction circuit is configured to receive the first output clock signal and the second output clock signal and to generate the set of control signal based on the first output clock signal and the second output clock signal.

    摘要翻译： 占空比检测和校正电路包括时钟发生器，时钟树和占空比校正电路。 时钟发生器被配置为产生第一时钟信号和第二时钟信号，并且第一时钟信号和第二时钟信号具有预定的相位差。 时钟树被配置为接收第一时钟信号和第二时钟信号，以基于第一时钟信号和该组控制信号产生第一输出时钟信号，并且基于第二时钟产生第二输出时钟信号 信号和控制信号的集合。 占空比校正电路被配置为接收第一输出时钟信号和第二输出时钟信号，并且基于第一输出时钟信号和第二输出时钟信号产生一组控制信号。