公开(公告)号：US08144517B2

公开(公告)日：2012-03-27

申请号：US12472033

申请日：2009-05-26

申请人： Doo Gon Kim ,  Ki Tae Park ,  Myoung Gon Kang

发明人： Doo Gon Kim ,  Ki Tae Park ,  Myoung Gon Kang

IPC分类号： G11C16/04

CPC分类号： G11C11/5621 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3454

摘要： A method and device for adaptive control of multilayered nonvolatile semiconductor memory are provided, the device including memory cells organized into groups and a control circuit having a look-up matrix for providing control parameters for each of the groups, where characteristics of each group are stored in the look-up matrix, and the control parameters for each group are responsive to the stored characteristics for that group; the method including organizing memory cells into groups, storing characteristics for each group in a look-up matrix, providing control parameters for each of the groups, where the control parameters for each group are responsive to its stored characteristics, and driving each memory cell in accordance with its provided control parameters.

摘要翻译： 提供了一种用于多层非易失性半导体存储器的自适应控制的方法和装置，该装置包括组织成组的存储单元和具有查找矩阵的控制电路，用于为存储每个组的特性的组中的每个组提供控制参数 在查找矩阵中，并且每个组的控制参数响应于该组的存储特性; 所述方法包括将存储器单元组合成组，将查找矩阵中的每个组存储特性，为每个组提供控制参数，其中每个组的控制参数响应于其存储的特性，以及驱动每个存储单元 根据其提供的控制参数。

公开(公告)号：US07933154B2

公开(公告)日：2011-04-26

申请号：US12213937

申请日：2008-06-26

申请人： Myoung Gon Kang ,  Ki Tae Park ,  Doo Gon Kim ,  Yeong Taek Lee

发明人： Myoung Gon Kang ,  Ki Tae Park ,  Doo Gon Kim ,  Yeong Taek Lee

IPC分类号： G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

摘要： A non-volatile memory device includes a memory cell array from which data is read via a plurality of bitlines, which includes a plurality of memory cells having gates respectively connected with a plurality of wordlines, a first type global wordline decoder configured to selectively apply n different voltages, where n is an integer greater than or equal to 3, to a corresponding wordline of the plurality of wordlines in a program mode, and a second type global wordline decoder configured to selectively apply (n−1) different voltages to a corresponding wordline of the plurality of wordlines in the program mode, the second type global wordline decoder having fewer switching elements than the first type global wordline decoder.

摘要翻译： 非易失性存储器件包括存储单元阵列，经由多个位线从其读取数据，存储单元阵列包括具有分别与多个字线连接的门的多个存储器单元，第一类型全局字线解码器，被配置为选择性地施加n 不同的电压，其中n是大于或等于3的整数，与程序模式中的多个字线的相应字线相对应，并且第二类型全局字线解码器被配置为选择性地将（n-1）个不同的电压应用于相应的 在编程模式下的多个字线的字线，第二类全局字线解码器具有比第一类全局字线解码器少的开关元件。

公开(公告)号：US20090273977A1

公开(公告)日：2009-11-05

申请号：US12472033

申请日：2009-05-26

申请人： Doo Gon Kim ,  Ki Tae Park ,  Myoung Gon Kang

发明人： Doo Gon Kim ,  Ki Tae Park ,  Myoung Gon Kang

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5621 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3454

摘要： A method and device for adaptive control of multilayered nonvolatile semiconductor memory are provided, the device including memory cells organized into groups and a control circuit having a look-up matrix for providing control parameters for each of the groups, where characteristics of each group are stored in the look-up matrix, and the control parameters for each group are responsive to the stored characteristics for that group; the method including organizing memory cells into groups, storing characteristics for each group in a look-up matrix, providing control parameters for each of the groups, where the control parameters for each group are responsive to its stored characteristics, and driving each memory cell in accordance with its provided control parameters.

摘要翻译： 提供了一种用于多层非易失性半导体存储器的自适应控制的方法和装置，该装置包括组织成组的存储单元和具有查找矩阵的控制电路，用于为存储每个组的特性的组中的每个组提供控制参数 在查找矩阵中，并且每个组的控制参数响应于该组的存储特性; 所述方法包括将存储器单元组合成组，将查找矩阵中的每个组存储特性，为每个组提供控制参数，其中每个组的控制参数响应于其存储的特性，以及驱动每个存储单元 根据其提供的控制参数。

公开(公告)号：US07848155B2

公开(公告)日：2010-12-07

申请号：US12165861

申请日：2008-07-01

申请人： Doo Gon Kim ,  Ki Tae Park ,  Yeong Taek Lee

发明人： Doo Gon Kim ,  Ki Tae Park ,  Yeong Taek Lee

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3404 ,  G11C16/349 ,  G11C29/82

摘要： Methods of operating non-volatile memory devices can compensate for threshold voltage disturbances caused by overhead data programming during block erase operations. These methods include erasing a spare array of nonvolatile memory cells and a corresponding main array of nonvolatile memory cells that shares word lines with the spare array. This erasing operation is followed by writing updated overhead data (e.g., an erase count) into the spare array and then performing a soft program operation. This soft program operation is performed on at least a first portion of the main array to thereby narrow a threshold voltage distribution of erased memory cells within the first portion of the main array. The soft program operation is then followed by an operation to verify an erased status of at least the first portion of the main array and an operation to communicate that the main and spare arrays of nonvolatile memory cells have been properly erased to a memory controller.

摘要翻译： 操作非易失性存储器件的方法可以补偿在块擦除操作期间由开销数据编程引起的阈值电压干扰。 这些方法包括擦除非易失性存储器单元的备用阵列和与备用阵列共享字线的非易失性存储单元的相应主阵列。 这种擦除操作之后是将更新的开销数据（例如，擦除计数）写入备用阵列中，然后执行软程序操作。 该软编程操作在主阵列的至少第一部分上执行，从而缩小主阵列的第一部分内的擦除的存储器单元的阈值电压分布。 然后，软程序操作之后是至少验证主阵列的第一部分的擦除状态的操作以及用于通知非易失性存储器单元的主阵列和备用阵列已经被适当地擦除到存储器控制器的操作。

公开(公告)号：US20090010073A1

公开(公告)日：2009-01-08

申请号：US12165861

申请日：2008-07-01

申请人： Doo Gon Kim ,  Ki Tae Park ,  Yeong Taek Lee

发明人： Doo Gon Kim ,  Ki Tae Park ,  Yeong Taek Lee

IPC分类号： G11C16/06 ,  G11C8/00

CPC分类号： G11C16/3404 ,  G11C16/349 ,  G11C29/82

摘要： Methods of operating non-volatile memory devices can compensate for threshold voltage disturbances caused by overhead data programming during block erase operations. These methods include erasing a spare array of nonvolatile memory cells and a corresponding main array of nonvolatile memory cells that shares word lines with the spare array. This erasing operation is followed by writing updated overhead data (e.g., an erase count) into the spare array and then performing a soft program operation. This soft program operation is performed on at least a first portion of the main array to thereby narrow a threshold voltage distribution of erased memory cells within the first portion of the main array. The soft program operation is then followed by an operation to verify an erased status of at least the first portion of the main array and an operation to communicate that the main and spare arrays of nonvolatile memory cells have been properly erased to a memory controller.

摘要翻译： 操作非易失性存储器件的方法可以补偿在块擦除操作期间由开销数据编程引起的阈值电压干扰。 这些方法包括擦除非易失性存储器单元的备用阵列和与备用阵列共享字线的非易失性存储单元的相应主阵列。 这种擦除操作之后是将更新的开销数据（例如，擦除计数）写入备用阵列中，然后执行软程序操作。 该软编程操作在主阵列的至少第一部分上执行，从而缩小主阵列的第一部分内的擦除的存储器单元的阈值电压分布。 然后，软程序操作之后是至少验证主阵列的第一部分的擦除状态的操作以及用于通知非易失性存储器单元的主阵列和备用阵列已经被适当地擦除到存储器控制器的操作。

公开(公告)号：US08427872B2

公开(公告)日：2013-04-23

申请号：US13008431

申请日：2011-01-18

申请人： Doo Gon Kim

发明人： Doo Gon Kim

IPC分类号： G11C11/34

CPC分类号： G11C29/781 ,  G11C29/765 ,  G11C29/80 ,  G11C29/82 ,  G11C29/846 ,  G11C2229/723 ,  H01L27/11582

摘要： A nonvolatile memory device comprises a main memory cell array, a redundancy memory cell array, and a controller. The main memory cell array comprises a plurality of bit lines each connected to a plurality of strings arranged perpendicular to a substrate. The redundancy memory cell array comprises a plurality of redundancy bit lines each connected to a plurality of redundancy strings arranged perpendicular to the substrate. The controller is configured to control one of the redundancy bit lines to repair strings in the main memory cell array.

摘要翻译： 非易失性存储器件包括主存储单元阵列，冗余存储单元阵列和控制器。 主存储单元阵列包括多个位线，每个位线连接到垂直于衬底布置的多个串。 冗余存储单元阵列包括多个冗余位线，每个冗余位线连接到垂直于衬底布置的多个冗余串。 控制器被配置为控制冗余位线之一来修复主存储单元阵列中的串。

公开(公告)号：US08451643B2

公开(公告)日：2013-05-28

申请号：US12775744

申请日：2010-05-07

申请人： Doo Gon Kim

发明人： Doo Gon Kim

IPC分类号： G11C11/00

CPC分类号： G11C13/0035 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C2013/0047 ,  G11C2213/72 ,  G11C2213/79

摘要： Provided is a semiconductor memory device including a memory cell; a writing driver providing a program current to the memory cell to write data in the memory cell; a sense amplifier processing a read operation reading data written in the memory cell; and a controller providing a rewriting signal for rewriting data read from the sense amplifier in the memory cell to the writing driver after the sense amplifier repeatedly applies a read operation more than a predetermined number of times.

摘要翻译： 提供一种包括存储单元的半导体存储器件; 写入驱动器向存储器单元提供程序电流以将数据写入存储单元; 读出放大器处理写入存储单元的读取操作读取数据; 以及控制器，在读出放大器反复地施加超过预定次数的读取操作之后，向写入驱动器提供用于将从存储单元中的读出放大器读取的数据重写的重写信号。

公开(公告)号：US20100290278A1

公开(公告)日：2010-11-18

申请号：US12775744

申请日：2010-05-07

申请人： Doo Gon Kim

发明人： Doo Gon Kim

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C13/0035 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C2013/0047 ,  G11C2213/72 ,  G11C2213/79

摘要： Provided is a semiconductor memory device including a memory cell; a writing driver providing a program current to the memory cell to write data in the memory cell; a sense amplifier processing a read operation reading data written in the memory cell; and a controller providing a rewriting signal for rewriting data read from the sense amplifier in the memory cell to the writing driver after the sense amplifier repeatedly applies a read operation more than a predetermined number of times.

摘要翻译： 提供一种包括存储单元的半导体存储器件; 写入驱动器向存储器单元提供程序电流以将数据写入存储单元; 读出放大器处理写入存储单元的读取操作读取数据; 以及控制器，在读出放大器反复地施加超过预定次数的读取操作之后，向写入驱动器提供用于将从存储单元中的读出放大器读取的数据重写的重写信号。