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公开(公告)号：US08699295B2
公开(公告)日：2014-04-15
申请号：US13564842
申请日：2012-08-02
Applicant: Myoung-Jin Lee , Jin-Hong An
Inventor： Myoung-Jin Lee , Jin-Hong An
CPC classification number: G11C8/08 , G11C11/4076 , G11C11/4085
Abstract: A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level.
Abstract translation: 半导体存储器件包括多个字线和驱动器，其被配置为当多个字线的字线被激活命令激活时，驱动与激活的字线相邻的至少一个非激活字线和具有不同的剩余非激活字线 在激活的字线被驱动到高电压电平的时间段内的字线驱动电压电平。
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公开(公告)号：US08593883B2
公开(公告)日：2013-11-26
申请号：US13564864
申请日：2012-08-02
Applicant: Myoung-Jin Lee , Jin-Hong An
Inventor： Myoung-Jin Lee , Jin-Hong An
IPC: G11C7/00
CPC classification number: G11C8/08 , G11C11/4076 , G11C11/4085
Abstract: A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level.
Abstract translation: 半导体存储器件包括多个字线和驱动器，其被配置为当多个字线的字线被激活命令激活时，驱动与激活的字线相邻的至少一个非激活字线和具有不同的剩余非激活字线 在激活的字线被驱动到高电压电平的时间段内的字线驱动电压电平。
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公开(公告)号：US08369124B2
公开(公告)日：2013-02-05
申请号：US12964182
申请日：2010-12-09
Applicant: Myoung Jin Lee
Inventor： Myoung Jin Lee
IPC: G11C5/06
Abstract: Disclosed is a semiconductor memory apparatus comprising an upper mat and a lower mat with a sense amplifier array region in between, where the sense amplifier array region includes a plurality of sense amplifiers. There is also a plurality of bit lines configured to extend toward the sense amplifier array region from the upper mat, and a plurality of complementary bit lines configured to extend toward the sense amplifier array region from the lower mat. Bit lines of the upper mat and complementary bit lines of the lower mat are configured to be alternately disposed at a predetermined interval in the sense amplifier array region, and the sense amplifier is configured to be formed between a bit line and a corresponding complementary bit line.
Abstract translation: 公开了一种半导体存储装置，包括上层和下层，其间具有读出放大器阵列区域，其中读出放大器阵列区域包括多个读出放大器。 还存在多个位线，其被配置为从上垫子朝着读出放大器阵列区域延伸，并且多个互补位线被配置为从下垫子朝着读出放大器阵列区域延伸。 上层的位线和下层的互补位线被配置为在感测放大器阵列区域中以预定间隔交替布置，并且读出放大器被配置为形成在位线和相应的互补位线 。
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公开(公告)号：US08259529B2
公开(公告)日：2012-09-04
申请号：US12544807
申请日：2009-08-20
Applicant: Myoung-Jin Lee , Jin-Hong An
Inventor： Myoung-Jin Lee , Jin-Hong An
CPC classification number: G11C8/08 , G11C11/4076 , G11C11/4085
Abstract: A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level.
Abstract translation: 半导体存储器件包括多个字线和驱动器，其被配置为当多个字线的字线被激活命令激活时，驱动与激活的字线相邻的至少一个非激活字线和具有不同的剩余非激活字线 在激活的字线被驱动到高电压电平的时间段内的字线驱动电压电平。
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公开(公告)号：US20120026773A1
公开(公告)日：2012-02-02
申请号：US12964182
申请日：2010-12-09
Applicant: Myoung Jin LEE
Inventor： Myoung Jin LEE
IPC: G11C5/06
Abstract: Disclosed is a semiconductor memory apparatus comprising an upper mat and a lower mat with a sense amplifier array region in between, where the sense amplifier array region includes a plurality of sense amplifiers. There is also a plurality of bit lines configured to extend toward the sense amplifier array region from the upper mat, and a plurality of complementary bit lines configured to extend toward the sense amplifier array region from the lower mat. Bit lines of the upper mat and complementary bit lines of the lower mat are configured to be alternately disposed at a predetermined interval in the sense amplifier array region, and the sense amplifier is configured to be formed between a bit line and a corresponding complementary bit line.
Abstract translation: 公开了一种半导体存储装置，包括上层和下层，其间具有读出放大器阵列区域，其中读出放大器阵列区域包括多个读出放大器。 还存在多个位线，其被配置为从上垫子朝着读出放大器阵列区域延伸，并且多个互补位线被配置为从下垫子朝着读出放大器阵列区域延伸。 上层的位线和下层的互补位线被配置为在感测放大器阵列区域中以预定间隔交替布置，并且读出放大器被配置为形成在位线和相应的互补位线 。
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Patent Agency Ranking
公开(公告)号：US20110128795A1
公开(公告)日：2011-06-02
申请号：US12649393
申请日：2009-12-30
Applicant: Myoung-Jin LEE , Hyung-Sik Won , Ki-Myung Kyung , Joong-Ho Lee
Inventor： Myoung-Jin LEE , Hyung-Sik Won , Ki-Myung Kyung , Joong-Ho Lee
CPC classification number: G11C7/02 , G11C7/065 , G11C7/08 , G11C11/4091
Abstract: A sense amplifier prevents a reduction in sensing margin occurring when data forms an island pattern. The sense amplifier includes a first inverter having an input terminal connected to a bit line and an output terminal connected to a bar bit line, and a second inverter having an input terminal connected to the bar bit line and an output terminal connected to the bit line. The first and second inverters are configured to receive a pull-up voltage through different pull-up voltage lines, respectively.
Abstract translation: 当数据形成岛状图案时，读出放大器可防止发生感测余量的减少。 读出放大器包括：第一反相器，其具有连接到位线的输入端和连接到条形位线的输出端;以及第二反相器，具有连接到条形位线的输入端和连接到位线的输出端 。 第一和第二反相器被配置为分别通过不同的上拉电压线接收上拉电压。
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公开(公告)号：US20110075495A1
公开(公告)日：2011-03-31
申请号：US12650446
申请日：2009-12-30
Applicant: Myoung Jin Lee , Ki Myung Kyung
Inventor： Myoung Jin Lee , Ki Myung Kyung
CPC classification number: G11C11/4074 , G11C7/02
Abstract: Various embodiments of a semiconductor memory apparatus and a related driving method are disclosed. According to one exemplary embodiment, a semiconductor memory apparatus may include a switching unit and a switching control unit. The switching unit couples or decouples a cell plate voltage line to or from a cell plate electrode in response to a control signal. The switching control unit is configured to enable the control signal at a first timing and disable the control signal at a second timing.
Abstract translation: 公开了半导体存储装置的各种实施例和相关的驱动方法。 根据一个示例性实施例，半导体存储器设备可以包括切换单元和切换控制单元。 开关单元响应于控制信号将单元板电压线与单元板电极耦合或去耦合。 切换控制单元被配置为在第一定时启用控制信号，并且在第二定时禁用控制信号。
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8.发明申请公开(公告)号：US20110051543A1
公开(公告)日：2011-03-03
申请号：US12648414
申请日：2009-12-29
Applicant: Myoung Jin LEE , Hyung Sik Won
Inventor： Myoung Jin LEE , Hyung Sik Won
Abstract: A semiconductor integrated circuit having a sense amplifier includes first and second inverters each having an output terminal coupled to an input terminal of the other inverter. The first inverter is configured to be activated in response to a first and a third activation signals, and the second inverter is configured to be activated in response to a second and a fourth activation signals. The first and third activation signals and the second and fourth activation signals are provided through separate signal sources from each other.
Abstract translation: 具有读出放大器的半导体集成电路包括第一和第二反相器，每个具有耦合到另一个反相器的输入端的输出端。 第一反相器被配置为响应于第一和第三激活信号被激活，并且第二反相器被配置为响应于第二和第四激活信号被激活。 第一和第三激活信号以及第二和第四激活信号通过彼此分离的信号源提供。
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公开(公告)号：US20100046313A1
公开(公告)日：2010-02-25
申请号：US12544807
申请日：2009-08-20
Applicant: Myoung-Jin LEE , Jin-Hong AN
Inventor： Myoung-Jin LEE , Jin-Hong AN
CPC classification number: G11C8/08 , G11C11/4076 , G11C11/4085
Abstract: A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level.
Abstract translation: 半导体存储器件包括多个字线和驱动器，其被配置为当多个字线的字线被激活命令激活时，驱动与激活的字线相邻的至少一个非激活字线和具有不同的剩余非激活字线 在激活的字线被驱动到高电压电平的时间段内的字线驱动电压电平。
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公开(公告)号：US20120314525A1
公开(公告)日：2012-12-13
申请号：US13564842
申请日：2012-08-02
Applicant: Myoung-Jin LEE , Jin-Hong AN
Inventor： Myoung-Jin LEE , Jin-Hong AN
CPC classification number: G11C8/08 , G11C11/4076 , G11C11/4085
Abstract: A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level.
Abstract translation: 半导体存储器件包括多个字线和驱动器，其被配置为当多个字线的字线被激活命令激活时，驱动与激活的字线相邻的至少一个非激活字线和具有不同的剩余非激活字线 在激活的字线被驱动到高电压电平的时间段内的字线驱动电压电平。
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