公开(公告)号：US08143692B2

公开(公告)日：2012-03-27

申请号：US12071847

申请日：2008-02-27

申请人： Myoung-jun Jang ,  Tae-soo Park

发明人： Myoung-jun Jang ,  Tae-soo Park

IPC分类号： H01L23/62

CPC分类号： H01L23/5223 ,  H01L23/525 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitance trimming circuit of a semiconductor device may include a plurality of capacitor layers and/or a plurality of fuses. The plurality of capacitor layers may be vertically stacked. The plurality of fuses may be arranged to correspond to the plurality of capacitor layers, and/or the plurality of fuses may be configured to select corresponding ones of the plurality of capacitor layers for controlling a capacitance of the plurality of capacitor layers.

摘要翻译： 半导体器件的电容微调电路可以包括多个电容器层和/或多个保险丝。 多个电容器层可以是垂直堆叠的。 多个保险丝可以被布置成对应于多个电容器层，和/或多个保险丝可以被配置为选择多个电容器层中的相应的保险丝来控制多个电容器层的电容。

公开(公告)号：US06242937B1

公开(公告)日：2001-06-05

申请号：US09306441

申请日：1999-05-06

申请人： Hi Deok Lee ,  Dae Mann Kim ,  Sang Gi Lee ,  Myoung Jun Jang

发明人： Hi Deok Lee ,  Dae Mann Kim ,  Sang Gi Lee ,  Myoung Jun Jang

IPC分类号： G01R3126

CPC分类号： G01R31/2849 ,  G01R31/2648

摘要： A hot carrier measuring circuit of the present invention, which measures the characteristic degradation of a semiconductor device due to AC operation, includes a pulse generator generating at least two pulse signals which are partially overlapped with each other and have various duty ratios, a level shifter shifting the pulse signal which are generated in the pulse generator to a desired voltage level, and a measuring device receiving the pulse signals outputted from the level shifter to at least one terminal thereof.

摘要翻译： 测量由于交流运行而导致的半导体器件的特性劣化的本发明的热载流子测量电路包括产生彼此部分重叠并具有各种占空比的至少两个脉冲信号的脉冲发生器，电平转换器 将在脉冲发生器中产生的脉冲信号移动到期望的电压电平;以及测量装置，将从电平移位器输出的脉冲信号接收到其至少一个端子。

公开(公告)号：US20080203525A1

公开(公告)日：2008-08-28

申请号：US12071847

申请日：2008-02-27

申请人： Myoung-jun Jang ,  Tae-soo Park

发明人： Myoung-jun Jang ,  Tae-soo Park

IPC分类号： H01L23/538 ,  H01L21/768

CPC分类号： H01L23/5223 ,  H01L23/525 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitance trimming circuit of a semiconductor device may include a plurality of capacitor layers and/or a plurality of fuses. The plurality of capacitor layers may be vertically stacked. The plurality of fuses may be arranged to correspond to the plurality of capacitor layers, and/or the plurality of fuses may be configured to select corresponding ones of the plurality of capacitor layers for controlling a capacitance of the plurality of capacitor layers.

摘要翻译： 半导体器件的电容微调电路可以包括多个电容器层和/或多个保险丝。 多个电容器层可以是垂直堆叠的。 多个保险丝可以被布置成对应于多个电容器层，和/或多个保险丝可以被配置为选择多个电容器层中的相应的保险丝来控制多个电容器层的电容。

公开(公告)号：US06569737B2

公开(公告)日：2003-05-27

申请号：US09818759

申请日：2001-03-28

申请人： Seong-Hyung Park ,  Myoung-Jun Jang

发明人： Seong-Hyung Park ,  Myoung-Jun Jang

IPC分类号： H01L21336

CPC分类号： H01L29/66621 ,  H01L21/76237

摘要： Forming a semiconductor transistor by embedding the gate electrode into the substrate so that a step difference between the gate electrode and the source or drain region is reduced. Device isolation areas are defined by forming at least two first trenches having a first depth. The gate electrode is formed in a second trench located between the first trenches at a second depth being less than the first depth. A source and a drain are respectively formed between the gate electrode and the device isolation areas. The gate electrically connects the source and drain to form a semiconductor channel in the substrate.

摘要翻译： 通过将栅电极嵌入衬底中形成半导体晶体管，使得栅电极和源极或漏极区之间的阶跃差减小。 通过形成具有第一深度的至少两个第一沟槽来限定器件隔离区域。 栅极电极形成在位于第一沟槽之间的第二沟槽中，第二沟槽的第二深度小于第一深度。 源极和漏极分别形成在栅电极和器件隔离区之间。 栅极电连接源极和漏极，以在衬底中形成半导体沟道。

公开(公告)号：US20070190811A1

公开(公告)日：2007-08-16

申请号：US11655222

申请日：2007-01-19

申请人： Sung-gyu Park ,  Myoung-jun Jang ,  Ji-young Shin

发明人： Sung-gyu Park ,  Myoung-jun Jang ,  Ji-young Shin

IPC分类号： H01L21/00

CPC分类号： G03F7/70466 ,  H01L21/67253

摘要： A method of forming a pattern for a semiconductor device includes forming first pattern data, forming second pattern data, forming third pattern data, forming pattern density measurement data including the first, second, and third pattern data, measuring a pattern density of the pattern density measurement data, adjusting shapes of patterns in the third pattern data based on a comparison of the measured density value and a reference density so as to form fourth pattern data, and forming final pattern data including the first, second, and fourth pattern data.

摘要翻译： 形成半导体器件的图案的方法包括形成第一图案数据，形成第二图案数据，形成第三图案数据，形成包括第一，第二和第三图案数据的图案密度测量数据，测量图案密度的图案密度 测量数据，基于测量的密度值和参考密度的比较来调整第三图案数据中的图案的形状，以形成第四图案数据，以及形成包括第一，第二和第四图案数据的最终图案数据。