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公开(公告)号：US6038116A
公开(公告)日：2000-03-14
申请号：US75449
申请日：1998-05-08
CPC分类号： H01L27/0251 , H01L27/0248
摘要： A high voltage input pad and method for accepting electrostatic discharge (ESD) surges without damage to an input semiconductor amplifier. The protection system includes a metal gate transistor, and n-well resistors which provide ESD protection. Protection is further provided against large voltages coupled to an amplifier by connecting an input bipolar junction transistor to the negative input connection of the amplifier. Negative surges are directed to ground with an anode grounded diode connected at its cathode to the negative input connection of the amplifier.
摘要翻译： 高压输入焊盘和接受静电放电（ESD）浪涌而不损坏输入半导体放大器的方法。 保护系统包括金属栅极晶体管和提供ESD保护的n阱电阻。 通过将输入双极结晶体管连接到放大器的负输入连接，进一步提供与放大器耦合的大电压的保护。 负极电流被引导到地，其阳极接地二极管在其阴极处连接到放大器的负输入连接。
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公开(公告)号：US06285536B1
公开(公告)日：2001-09-04
申请号：US09433812
申请日：1999-11-03
IPC分类号： H02H900
CPC分类号： H01L27/0251 , H01L27/0248
摘要： A high voltage input pad and method for accepting electrostatic discharge (ESD) surges without damage to an input semiconductor amplifier. The protection system includes a metal gate, transistor, and n-well resistors which provide ESD protection. Protection is further provided against large voltages coupled to an amplifier by connecting an input bipolar junction transistor to the negative input connection of the amplifier. Negative surges are directed to ground with an anode grounded diode connected at its cathode to the negative input connection of the amplifier.
摘要翻译： 高压输入焊盘和接受静电放电（ESD）浪涌而不损坏输入半导体放大器的方法。 保护系统包括提供ESD保护的金属栅极，晶体管和n阱电阻。 通过将输入双极结晶体管连接到放大器的负输入连接，进一步提供与放大器耦合的大电压的保护。 负极电流被引导到地，其阳极接地二极管在其阴极处连接到放大器的负输入连接。
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公开(公告)号：US07304679B1
公开(公告)日：2007-12-04
申请号：US10742170
申请日：2003-12-19
CPC分类号： H03M1/002 , H03M1/007 , H03M1/12 , H04N5/232 , H04N5/23245
摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.
摘要翻译： 用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以使数据分辨率降低 预览显示器，具有可选择的窄位宽输出并耦合到所述VGA电路的低功率模式模数转换器（ADC）以及耦合到所述ADC的增益电路。 单芯片低功耗模拟前端以第一电流电平以13位，12位或10位格式生成数字化CCD数据，并以第二个电流产生9位，8位或6位格式 水平。 VGA放大器包括对称的子电路，它们独立地可启动，以分别在单独的预览屏幕上实现静态图像捕获操作和视频预览的全部或者简化的数据分辨率级别。
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公开(公告)号：US07719595B1
公开(公告)日：2010-05-18
申请号：US11980173
申请日：2007-10-30
CPC分类号： H03M1/002 , H03M1/007 , H03M1/12 , H04N5/232 , H04N5/23245
摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.
摘要翻译： 用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以使数据分辨率降低 预览显示器，具有可选择的窄位宽输出并耦合到所述VGA电路的低功率模式模数转换器（ADC）以及耦合到所述ADC的增益电路。 单芯片低功耗模拟前端以第一电流电平以13位，12位或10位格式生成数字化CCD数据，并以第二个电流产生9位，8位或6位格式 水平。 VGA放大器包括对称的子电路，它们独立地可启动，以分别在单独的预览屏幕上实现静态图像捕获操作和视频预览的全部或者简化的数据分辨率级别。
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公开(公告)号：US06686957B1
公开(公告)日：2004-02-03
申请号：US09282524
申请日：1999-03-31
IPC分类号： H04N5228
CPC分类号： H03M1/002 , H03M1/007 , H03M1/12 , H04N5/232 , H04N5/23245
摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.
摘要翻译： 用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以使数据分辨率降低 预览显示器，具有可选择的窄位宽输出并耦合到所述VGA电路的低功率模式模数转换器（ADC），以及耦合到所述ADC的增益电路。 单芯片低功耗模拟前端以第一电流电平以13位，12位或10位格式生成数字化CCD数据，并以第二个电流产生9位，8位或6位格式 水平。 VGA放大器包括对称的子电路，它们独立地可启动，以分别在单独的预览屏幕上实现静态图像捕获操作和视频预览的全部或者简化的数据分辨率级别。
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公开(公告)号：US07286176B2
公开(公告)日：2007-10-23
申请号：US10820577
申请日：2004-04-08
CPC分类号： H04N5/23241 , H04N5/23293 , H04N5/335
摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sample and variable gain (CDS/VGA) circuit for receiving data from a CCD system, subject to horizontal and vertical timing signals for the system which are locally generated by the processing system itself. The processing system particularly includes programmable timing circuitry for controlling the detection of pixel intensity values from elements of a two-dimensional pixel array, with a programmable low-frequency master vertical timing circuit driving a high-frequency horizontal timing circuit, wherein the vertical and horizontal timing signals are independently locally provided to the array from the analog processor actually sampling the array. The architecture of the processing system further includes a correlated double sampler, a black level clamp, and an A/D conversion module. The processing system includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution, an analog-to-digital converter (ADC) having a selectable bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip analog front end produces digitized CCD data in a bit formats corresponding to selected current level and data resolution. The VGA amplifier includes circuitry to enable selected data resolution levels respectively for still image capture and separate video display on another viewing screen.
摘要翻译： 用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括多模，多电流电平，相关双样本和可变增益（CDS / VGA）电路，用于从CCD系统接收数据，受水平和垂直 由处理系统本身本地生成的系统的定时信号。 处理系统特别地包括可编程定时电路，用于通过驱动高频水平定时电路的可编程低频主垂直定时电路来控制来自二维像素阵列的元件的像素强度值的检测，其中垂直和水平 定时信号从模拟处理器独立地本地提供给阵列，实际上对阵列进行采样。 处理系统的架构还包括相关双采样器，黑电平钳位器和A / D转换模块。 该处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以实现减少的数据分辨率; 具有可选位宽输出并耦合到所述VGA电路的数模转换器（ADC），以及耦合到所述ADC的增益电路。 单芯片模拟前端以对应于所选电流和数据分辨率的位格式生成数字化CCD数据。 VGA放大器包括分别为静止图像拍摄和在另一个观看屏幕上分离的视频显示启用所选数据分辨率级别的电路。
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公开(公告)号：US06720999B1
公开(公告)日：2004-04-13
申请号：US09283112
申请日：1999-03-31
IPC分类号： H04N5228
CPC分类号： H04N5/23241 , H04N5/23293 , H04N5/335
摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sample and variable gain (CDS/VGA) circuit for receiving data from a CCD system, subject to horizontal and vertical timing signals for the system which are locally generated by the processing system itself. The processing system particularly includes programmable timing circuitry for controlling the detection of pixel intensity values from elements of a two-dimensional pixel array, with a programable low-frequency master vertical timing circuit driving a high-frequency horizontal timing circuit, wherein the vertical and horizontal timing signals are independently locally provided to the array from the analog processor actually sampling the array. The architecture of the processing system further includes a correlated double sampler, a black level clamp, and an A/D conversion module. The processing system includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution, an analog-to-digital converter (ADC) having a selectable bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip analog front end produces digitized CCD data in a bit formats corresponding to selected current level and data resolution. The VGA amplifier includes circuitry to enable selected data resolution levels respectively for still image capture and separate video display on another viewing screen.
摘要翻译： 用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括多模，多电流电平，相关双样本和可变增益（CDS / VGA）电路，用于从CCD系统接收数据，受水平和垂直 由处理系统本身本地生成的系统的定时信号。 处理系统特别地包括可编程定时电路，用于通过驱动高频水平定时电路的可编程低频主垂直定时电路来控制来自二维像素阵列的元件的像素强度值的检测，其中垂直和水平 定时信号从模拟处理器独立地本地提供给阵列，实际上对阵列进行采样。 处理系统的架构还包括相关双采样器，黑电平钳位器和A / D转换模块。 该处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以实现减少的数据分辨率; 具有可选位宽输出并耦合到所述VGA电路的数模转换器（ADC），以及耦合到所述ADC的增益电路。 单芯片模拟前端以对应于所选电流和数据分辨率的位格式生成数字化CCD数据。 VGA放大器包括分别为静止图像拍摄和在另一个观看屏幕上分离的视频显示启用所选数据分辨率级别的电路。
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8.发明授权Correlated double sampling variable gain amplifier circuit for use in a digital camera 有权用于数码相机的相关双倍可变增益放大器电路公开(公告)号：US07289145B2
公开(公告)日：2007-10-30
申请号：US11415000
申请日：2006-05-01
申请人： Sandra Marie Johnson , Shih-Chung Chao , Nadi Rafik Itani , Caiyi Wang , Brannon Craig Harris , Ash Prabala , Douglas R. Holberg , Alan Hansford , Syed Khalid Azim , David R. Welland
发明人： Sandra Marie Johnson , Shih-Chung Chao , Nadi Rafik Itani , Caiyi Wang , Brannon Craig Harris , Ash Prabala , Douglas R. Holberg , Alan Hansford , Syed Khalid Azim , David R. Welland
IPC分类号： H04N5/235
CPC分类号： H04N5/3575 , H04N5/335 , H04N5/361
摘要： An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.
摘要翻译： 用于电荷耦合器件（CCD）或CMOS成像系统的图像处理器系统包括用于从CCD系统接收数据的相关双样本和可变增益（CDSVGA）电路以及首先通过调整来控制增益的自动增益控制（AGC）电路 所述CCD系统然后为了更高的增益水平，使得所述CDSVGA电路和数字增益电路中的增益调整产生组合的目标增益电平。 一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC） 耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路。 处理电路包括模拟前端和数字信号处理系统，用于捕获全运动视频并输出CCIR 601 4：2：2 YCrCb视频数据输出以便呈现在用户选择的显示器上。
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公开(公告)号：US07256611B2
公开(公告)日：2007-08-14
申请号：US11005700
申请日：2004-12-07
IPC分类号： H03K19/177
CPC分类号： H03K19/1731
摘要： A cross-bar matrix includes a plurality of matrix cells arranged in rows and columns wherein each row of cells is associated with a signal input and each column of cells is associated with a common signal output. An enable input controls whether at least a portion of the cells couple a signal on the associated common signal input to a signal output associated with a cell or couple an LCD signal to a signal output and exclude control of the at least portion of said plurality of cells by the control input.
摘要翻译： 交叉矩阵矩阵包括以行和列排列的多个矩阵单元，其中每行单元与信号输入相关联，并且每列单元与公共信号输出相关联。 使能输入控制是否至少一部分单元将相关联的公共信号输入上的信号耦合到与单元相关联的信号输出或将LCD信号耦合到信号输出，并且排除对所述多个 单元由控制输入。
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公开(公告)号：US06879004B2
公开(公告)日：2005-04-12
申请号：US10288188
申请日：2002-11-05
申请人： Ka Y. Leung , Douglas R. Holberg
发明人： Ka Y. Leung , Douglas R. Holberg
IPC分类号： H01L23/62
CPC分类号： H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： A spark gap device for protecting an integrated circuit. The spark gap device includes a first node for receiving an input signal and a second node to be protected. A first conductive layer is conductively interfaced to the first node and the second node and disposed therebetween. A second conductive layer is connected to a sink voltage and separated from the first conductive layer by an insulating layer of a predetermined thickness. A portion of the first conductive layer is disposed proximate to the second conductive layer and not overlying the second conductive layer, such that a gap is formed therebetween and the gap having a dimension that is greater than the thickness of the insulating layer.
摘要翻译： 一种用于保护集成电路的火花隙装置。 火花隙装置包括用于接收输入信号的第一节点和待保护的第二节点。 第一导电层导电地接合到第一节点和第二节点并且设置在它们之间。 第二导电层连接到宿电压，并通过预定厚度的绝缘层与第一导电层分离。 第一导电层的一部分设置成靠近第二导电层并且不覆盖第二导电层，使得在其间形成间隙，并且间隙的尺寸大于绝缘层的厚度。
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