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    Methods for fabricating ferroelectric memory devices with improved ferroelectric properties
    2.
    发明授权
    Methods for fabricating ferroelectric memory devices with improved ferroelectric properties 有权
    具有改进的铁电性能的制造铁电存储器件的方法

    公开(公告)号：US07488628B2

    公开(公告)日：2009-02-10

    申请号：US11384689

    申请日：2006-03-20

    申请人： Yoon-Jong Song ,  Nak-Won Jang ,  Ki-Nam Kim

    发明人： Yoon-Jong Song ,  Nak-Won Jang ,  Ki-Nam Kim

    IPC分类号： H01L21/00 ,  H01L21/335 ,  H01L21/8232 ,  H01L21/8242

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

    摘要： Pursuant to embodiments of the present invention, ferroelectric memory devices are provided which comprise a transistor that is provided on an active region in a semiconductor substrate, and a capacitor that has a bottom electrode, a capacitor-ferroelectric layer and a top electrode. These devices may further include at least one planarizing layer that is adjacent to the side surfaces of the bottom electrode such that the top surface of the planarizing layer(s) and the top surface of the bottom electrode form a planar surface. The capacitor-ferroelectric may be formed on this planar surface. The device may also include a plug that electrically connects the bottom electrode to a source-drain region of the transistor. The ferroelectric memory devices according to embodiments of the present invention may reduce ferroelectric degradation of the capacitor.

    摘要翻译： 根据本发明的实施例，提供了包括设置在半导体衬底中的有源区上的晶体管和具有底电极，电容器 - 铁电层和顶电极的电容器的铁电存储器件。 这些装置还可以包括与底部电极的侧表面相邻的至少一个平坦化层，使得平坦化层的顶表面和底部电极的顶表面形成平坦的表面。 电容器 - 铁电体可以形成在该平坦表面上。 器件还可以包括将底部电极电连接到晶体管的源极 - 漏极区域的插头。 根据本发明实施例的铁电存储器件可以减小电容器的铁电性能降低。

    Methods for fabricating ferroelectric memory devices with improved ferroelectric properties
    3.
    发明申请
    Methods for fabricating ferroelectric memory devices with improved ferroelectric properties 有权

    公开(公告)号：US20060160252A1

    公开(公告)日：2006-07-20

    申请号：US11384689

    申请日：2006-03-20

    申请人： Yoon-Jong Song ,  Nak-Won Jang ,  Ki-Nam Kim

    发明人： Yoon-Jong Song ,  Nak-Won Jang ,  Ki-Nam Kim

    IPC分类号： H01L21/00 ,  H01L21/8242

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

    摘要： Pursuant to embodiments of the present invention, ferroelectric memory devices are provided which comprise a transistor that is provided on an active region in a semiconductor substrate, and a capacitor that has a bottom electrode, a capacitor-ferroelectric layer and a top electrode. These devices may further include at least one planarizing layer that is adjacent to the side surfaces of the bottom electrode such that the top surface of the planarizing layer(s) and the top surface of the bottom electrode form a planar surface. The capacitor-ferroelectric may be formed on this planar surface. The device may also include a plug that electrically connects the bottom electrode to a source-drain region of the transistor. The ferroelectric memory devices according to embodiments of the present invention may reduce ferroelectric degradation of the capacitor.

    Ferroelectric memory devices having an expanded plate electrode
    4.
    发明授权
    Ferroelectric memory devices having an expanded plate electrode 失效
    具有扩展板电极的铁电存储器件

    公开(公告)号：US07064366B2

    公开(公告)日：2006-06-20

    申请号：US10787424

    申请日：2004-02-26

    申请人： Hyun-Yul Kang ,  Yoon-Jong Song ,  Nak-Won Jang

    发明人： Hyun-Yul Kang ,  Yoon-Jong Song ,  Nak-Won Jang

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： G11C11/22 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507

    摘要： Ferroelectric memory devices are formed on an integrated circuit substrate. A bottom interlayer dielectric layer is positioned on the integrated circuit substrate and a plurality of ferroelectric capacitors are arranged in a row and column relationship on the bottom interlayer dielectric layer. A top interlayer dielectric layer is disposed on a surface of the integrated circuit substrate including the plurality of ferroelectric capacitors. The top interlayer dielectric layer includes via holes disposed on and associated with ones of the ferroelectric capacitors. A plate electrode is formed in the top interlayer dielectric layer. The plate electrode extends into respective ones of the via holes to contact top surfaces of at least two neighboring ones of the plurality of ferroelectric capacitors. Methods or fabricating ferroelectric memory devices are also provided.

    摘要翻译： 铁电存储器件形成在集成电路衬底上。 底层间介质层位于集成电路基板上，并且多个铁电电容器以行和列关系布置在底层间介质层上。 在包括多个铁电电容器的集成电路基板的表面上设置顶层间介质层。 顶层间介质层包括布置在铁电电容器之一上并与其相关联的通孔。 在顶层间介质层中形成平板电极。 板电极延伸到相应的通孔中以接触多个铁电电容器中的至少两个相邻的电介质电容器的顶表面。 还提供了方法或制造铁电存储器件。

    Ferroelectric memory devices with improved ferroelectric properties and associated methods for fabricating such memory devices
    5.
    发明授权
    Ferroelectric memory devices with improved ferroelectric properties and associated methods for fabricating such memory devices 失效
    具有改进的铁电性能的铁电存储器件和用于制造这种存储器件的相关方法

    公开(公告)号：US07045839B2

    公开(公告)日：2006-05-16

    申请号：US10775016

    申请日：2004-02-10

    申请人： Yoon-Jong Song ,  Nak-Won Jang ,  Ki-Nam Kim

    发明人： Yoon-Jong Song ,  Nak-Won Jang ,  Ki-Nam Kim

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

    摘要： Pursuant to embodiments of the present invention, ferroelectric memory devices are provided which comprise a transistor that is provided on an active region in a semiconductor substrate, and a capacitor that has a bottom electrode, a capacitor-ferroelectric layer and a top electrode. These devices may further include at least one planarizing layer that is adjacent to the side surfaces of the bottom electrode such that the top surface of the planarizing layer(s) and the top surface of the bottom electrode form a planar surface. The capacitor-ferroelectric may be formed on this planar surface. The device may also include a plug that electrically connects the bottom electrode to a source-drain region of the transistor. The ferroelectric memory devices according to embodiments of the present invention may reduce ferroelectric degradation of the capacitor.

    摘要翻译： 根据本发明的实施例，提供了包括设置在半导体衬底中的有源区上的晶体管和具有底电极，电容器 - 铁电层和顶电极的电容器的铁电存储器件。 这些装置还可以包括与底部电极的侧表面相邻的至少一个平坦化层，使得平坦化层的顶表面和底部电极的顶表面形成平坦的表面。 电容器 - 铁电体可以形成在该平坦表面上。 器件还可以包括将底部电极电连接到晶体管的源极 - 漏极区域的插头。 根据本发明实施例的铁电存储器件可以减小电容器的铁电性能降低。

    Ferroelectric memory devices with improved ferroelectric properties and associated methods for fabricating such memory devices
    6.
    发明申请
    Ferroelectric memory devices with improved ferroelectric properties and associated methods for fabricating such memory devices 失效
    具有改进的铁电性能的铁电存储器件和用于制造这种存储器件的相关方法

    公开(公告)号：US20050006680A1

    公开(公告)日：2005-01-13

    申请号：US10775016

    申请日：2004-02-10

    申请人： Yoon-Jong Song ,  Nak-Won Jang ,  Ki-Nam Kim

    发明人： Yoon-Jong Song ,  Nak-Won Jang ,  Ki-Nam Kim

    IPC分类号： H01L27/105 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

    摘要： Pursuant to embodiments of the present invention, ferroelectric memory devices are provided which comprise a transistor that is provided on an active region in a semiconductor substrate, and a capacitor that has a bottom electrode, a capacitor-ferroelectric layer and a top electrode. These devices may further include at least one planarizing layer that is adjacent to the side surfaces of the bottom electrode such that the top surface of the planarizing layer(s) and the top surface of the bottom electrode form a planar surface. The capacitor-ferroelectric may be formed on this planar surface. The device may also include a plug that electrically connects the bottom electrode to a source-drain region of the transistor. The ferroelectric memory devices according to embodiments of the present invention may reduce ferroelectric degradation of the capacitor.

    摘要翻译： 根据本发明的实施例，提供了包括设置在半导体衬底中的有源区上的晶体管和具有底电极，电容器 - 铁电层和顶电极的电容器的铁电存储器件。 这些装置还可以包括与底部电极的侧表面相邻的至少一个平坦化层，使得平坦化层的顶表面和底部电极的顶表面形成平坦的表面。 电容器 - 铁电体可以形成在该平坦表面上。 器件还可以包括将底部电极电连接到晶体管的源极 - 漏极区域的插头。 根据本发明实施例的铁电存储器件可以减小电容器的铁电性能降低。