公开(公告)号：US06728258B1

公开(公告)日：2004-04-27

申请号：US09456383

申请日：1999-12-08

申请人： Tetsuhiko Okada ,  Naoki Hamanaka ,  Naohiko Irie ,  Takehisa Hayashi ,  Tetsuya Mochida ,  Masabumi Shibata ,  Youichi Tanaka ,  Yasuhiro Ishii

发明人： Tetsuhiko Okada ,  Naoki Hamanaka ,  Naohiko Irie ,  Takehisa Hayashi ,  Tetsuya Mochida ,  Masabumi Shibata ,  Youichi Tanaka ,  Yasuhiro Ishii

IPC分类号： H04L1266

CPC分类号： G06F15/17375 ,  G06F12/0833 ,  G06F2212/1016 ,  G06F2212/206

摘要： In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.

摘要翻译： 在通过具有多个端口的交叉开关连接到处理器单元，存储器单元和连接到输入/输出设备的输入/输出单元的多处理器系统中，每个处理器单元的发射器具有用于确定接入的目的地的电路 请求以下列方式。 对于对主存储器的访问请求，访问请求被传送到存储要访问的数据的所有处理器单元和一个存储单元。 对于对输入/输出设备的存储器映射寄存器的访问请求，将访问请求广播到所有输入/输出单元。 对于属于处理器单元，存储器单元和输入/输出单元中的任何一个的存储器映射寄存器的访问请求，访问请求经由交叉开关广播到所有单元。

公开(公告)号：US6011791A

公开(公告)日：2000-01-04

申请号：US747344

申请日：1996-11-12

申请人： Tetsuhiko Okada ,  Naoki Hamanaka ,  Naohiko Irie ,  Takehisa Hayashi ,  Tetsuya Mochida ,  Masabumi Shibata ,  Youichi Tanaka ,  Yasuhiro Ishii

发明人： Tetsuhiko Okada ,  Naoki Hamanaka ,  Naohiko Irie ,  Takehisa Hayashi ,  Tetsuya Mochida ,  Masabumi Shibata ,  Youichi Tanaka ,  Yasuhiro Ishii

IPC分类号： G06F15/173 ,  G06F13/38 ,  H04L12/56

CPC分类号： G06F15/17375

摘要： In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.

摘要翻译： 在通过具有多个端口的交叉开关连接到处理器单元，存储器单元和连接到输入/输出设备的输入/输出单元的多处理器系统中，每个处理器单元的发射器具有用于确定接入的目的地的电路 请求以下列方式。 对于对主存储器的访问请求，访问请求被传送到存储要访问的数据的所有处理器单元和一个存储单元。 对于对输入/输出设备的存储器映射寄存器的访问请求，将访问请求广播到所有输入/输出单元。 对于属于处理器单元，存储器单元和输入/输出单元中的任何一个的存储器映射寄存器的访问请求，访问请求经由交叉开关广播到所有单元。

公开(公告)号：US6038644A

公开(公告)日：2000-03-14

申请号：US820831

申请日：1997-03-19

申请人： Naohiko Irie ,  Naoki Hamanaka ,  Masabumi Shibata

发明人： Naohiko Irie ,  Naoki Hamanaka ,  Masabumi Shibata

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0833

摘要： Information indicative of whether each processor unit caches data which belongs to each of the plural areas of the main memory larger than a cache line is stored in the multicast table. The destinations of a coherent processing request which should be sent to other processor units are limited by the information stored in this table. The interconnection network broadcasts the request to the limited destinations. When the processor unit of the destination of this processing request sends back a cache status of the data designated by the request, it also sends back the caching status in the processor unit concerning a specific memory area which includes the data. Depending on this send back, the request source processor unit renews a portion relating to the destination processor unit within the caching status concerning that specific memory area stored in the processor unit.

摘要翻译： 指示每个处理器单元是否将属于主存储器的多个区域中的每一个的数据高于高速缓存行的信息存储在多播表中。 应发送到其他处理器单元的相干处理请求的目的地受到该表中存储的信息的限制。 互连网络将请求广播到有限的目的地。 当该处理请求的目的地的处理器单元发送由请求指定的数据的高速缓存状态时，它还将处理器单元中的缓存状态发送回包括该数据的特定存储器区域。 根据该发送回来，请求源处理器单元在关于存储在处理器单元中的特定存储器区域的高速缓存状态内更新与目的地处理器单元相关的部分。

公开(公告)号：US06263405B1

公开(公告)日：2001-07-17

申请号：US09134336

申请日：1998-08-14

申请人： Naohiko Irie ,  Naoki Hamanaka ,  Tsuyoshi Tanaka ,  Masabumi Shibata ,  Atsushi Nakajima

发明人： Naohiko Irie ,  Naoki Hamanaka ,  Tsuyoshi Tanaka ,  Masabumi Shibata ,  Atsushi Nakajima

IPC分类号： G06F1212

CPC分类号： G06F12/0815 ,  G06F12/0813

摘要： A cache status report sum up for use in a multiprocessor system having a plurality of processor units each having a processor and a cache memory and a plurality of memory units. The cache status report sum up apparatus sums up cache coherency check results indicating statuses of the cache memories without limiting the number of memory access requests requiring cache coherency checks that can be overlapped when the memory access requests requiring cache coherency checks are executed in an overlapping manner. The cache status report sum up apparatus is provided between the processor units and the memory units and sums up cache coherency check results sent by cache status reporting apparatus included in each processor unit. The cache status reporting apparatus responds to a memory access request requiring a cache coherency check. The cache status report sum up apparatus, after summing up the cache coherency check results, sends the summary of the cache coherency check results to the processor unit which requested the memory access request requiring a cache coherency check.

摘要翻译： 高速缓存状态报告总结为在具有多个处理器单元的多处理器系统中使用，每个处理器单元各自具有处理器和高速缓冲存储器以及多个存储器单元。 高速缓存状态报告总结装置总结高速缓存一致性检查结果，指示高速缓存存储器的状态，而不限制需要高速缓存一致性检查的存储器访问请求的数量，当需要高速缓存一致性检查的存储器访问请求以重叠的方式执行时可重叠 。 在处理器单元和存储器单元之间提供高速缓存状态报告总结装置，并且对由每个处理器单元中包括的高速缓存状态报告装置发送的高速缓存一致性检查结果求和。 高速缓存状态报告装置响应需要高速缓存一致性检查的存储器访问请求。 高速缓存状态报告总结装置在总结高速缓存一致性检查结果之后，将高速缓存一致性检查结果的摘要发送到请求需要高速缓存一致性检查的存储器访问请求的处理器单元。

公开(公告)号：US06298418B1

公开(公告)日：2001-10-02

申请号：US08975671

申请日：1997-11-28

申请人： Shisei Fujiwara ,  Masabumi Shibata ,  Atsushi Nakajima ,  Naoki Hamanaka ,  Naohiko Irie

发明人： Shisei Fujiwara ,  Masabumi Shibata ,  Atsushi Nakajima ,  Naoki Hamanaka ,  Naohiko Irie

IPC分类号： G06F1208

CPC分类号： G06F12/0833

摘要： In a bus or switch coupled system having a plurality of processor modules and a memory module, the memory module is provided with a unit for returning a write completion acknowledgement (WRITE_ACK) to a write requesting processor module. If a processor module PM1 is under execution of write-back of a cache line upon arrival of a cache coherence check (CCC) issued from a processor module with a cache miss of the cache line, an “INVALID” signal is returned to the CCC issued processor module PMO after a write completion acknowledgment from the memory module is confirmed and the cache line is invalidated. After confirming the “INVALID” signals from other processor modules, the CCC issued processor module issues a READ transaction to the memory module to obtain correct latest data reflecting the write-back data of the processor module.

摘要翻译： 在具有多个处理器模块和存储器模块的总线或开关耦合系统中，存储器模块设置有用于将写入完成确认（WRITE_ACK）返回到写入请求处理器模块的单元。 如果处理器模块PM1在从具有高速缓存行的高速缓存未命中的处理器模块发出的高速缓存一致性检查（CCC）到达时执行高速缓存行的写回，则将“INVALID”信号返回给CCC 在从存储器模块进行写入完成确认之后，发出的处理器模块PMO被确认并且高速缓存行无效。 在确认来自其他处理器模块的“INVALID”信号后，CCC发出的处理器模块向存储器模块发出READ事务，以获得反映处理器模块的回写数据的正确的最新数据。

公开(公告)号：US07206818B2

公开(公告)日：2007-04-17

申请号：US10632856

申请日：2003-08-04

申请人： Toshio Okochi ,  Toru Shonai ,  Naoki Hamanaka ,  Naohiko Irie ,  Hideya Akashi

发明人： Toshio Okochi ,  Toru Shonai ,  Naoki Hamanaka ,  Naohiko Irie ,  Hideya Akashi

IPC分类号： G06F15/167

CPC分类号： G06F15/167 ,  G06F2212/682

摘要： Multiprocessor system, having a translation lookaside buffer (TLB) in each processor, and having a structure for avoiding TLB purge overhead. Each processor node is provided with a partial main memory and a physical page map table (PPT). The PPT stores mapping between physical page number of main memory and virtual page number. Every memory access transaction for other node specifies physical address and virtual page number. Instead of strictly maintaining TLB coherency by broadcasting TLB purge transaction, an access destination node checks the coincidence between the virtual page number specified in the memory access transaction and the virtual page number mapped in the PPT when the transaction is received. If both are coincident, the memory access is executed. If not coincident, an error message is transferred to an access requesting source.

摘要翻译： 在每个处理器中具有翻译后备缓冲器（TLB）的多处理器系统，并具有用于避免TLB清除开销的结构。 每个处理器节点设置有部分主存储器和物理页映射表（PPT）。 PPT存储主存储器的物理页数和虚拟页码之间的映射。 其他节点的每个内存访问事务都指定物理地址和虚拟页码。 访问目的地节点不是通过广播TLB清除事务来严格维护TLB一致性，而是在接收事务时检查在存储器访问事务中指定的虚拟页号与在PPT中映射的虚拟页号之间的一致性。 如果两者都一致，则执行存储器访问。 如果不一致，则将错误消息传送到请求访问源。

公开(公告)号：US07493479B2

公开(公告)日：2009-02-17

申请号：US10458289

申请日：2003-06-11

申请人： Masayuki Kabasawa ,  Naohiko Irie ,  Takahiro Irita ,  Tetsuya Yamada ,  Takanobu Tsunoda

发明人： Masayuki Kabasawa ,  Naohiko Irie ,  Takahiro Irita ,  Tetsuya Yamada ,  Takanobu Tsunoda

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00 ,  G06F7/38

CPC分类号： G06F9/30174 ,  G06F9/3851

摘要： A method and apparatus are provided for event detection for a multiple instruction-set processor. In one example of the apparatus, a data processing device comprises an instruction execution device configured to execute a first instruction set as specific instructions; an instruction conversion circuit configured to convert instructions of a second instruction set into a first instruction string of the first instruction set, and further configured to supply the first instruction string to the instruction execution device; and a counter device configured to count a prescribed event, wherein the instruction conversion circuit is further configured to output a prescribed instruction when the counter device is satisfied by a prescribed condition.

摘要翻译： 提供了一种用于多指令集处理器的事件检测的方法和装置。 在该装置的一个示例中，数据处理装置包括被配置为执行第一指令集作为特定指令的指令执行装置; 指令转换电路，被配置为将第二指令集的指令转换为第一指令集的第一指令串，并且还被配置为将第一指令串提供给指令执行装置; 以及计数器装置，被配置为对规定的事件进行计数，其中所述指令转换电路还被配置为当所述计数器装置满足规定条件时输出规定的指令。

公开(公告)号：US07340078B2

公开(公告)日：2008-03-04

申请号：US10876596

申请日：2004-06-28

申请人： Hiroaki Shikano ,  Naohiko Irie

发明人： Hiroaki Shikano ,  Naohiko Irie

IPC分类号： G06K9/00

CPC分类号： G06K9/00664

摘要： Disclosed here is an information processing system capable of recognizing actions and circumstances of a user with respect to both space and time as a “situation” to recognize the user's request using a plurality of sensing nodes that work cooperatively with each another, thereby responding autonomously to the user's request according to the recognition results. The plurality of sensing nodes and a responding device are disposed in a target space to build up a network for recognizing the situation in the target space. And, a plurality of recognition means are used to recognize the situation with respect to both space and time related to the existence of the user. And, an integral processing portion (master) is selected from among the plurality of sensing nodes, thereby dispersing the system load. If there are a plurality of users, the system can make recognition in accordance with the request of each of those users.

摘要翻译： 这里公开了一种信息处理系统，其能够将用户相对于空间和时间的动作和情况识别为使用多个彼此协作工作的感测节点来识别用户的请求的“情况”，从而自主地响应于 用户的请求根据识别结果。 多个感测节点和响应装置设置在目标空间中以构建用于识别目标空间中的情况的网络。 并且，使用多个识别装置来识别与用户的存在相关的空间和时间的情况。 并且，从多个感测节点中选择积分处理部（主），从而分散系统负载。 如果存在多个用户，则系统可以根据每个用户的请求进行识别。

公开(公告)号：US20070284619A1

公开(公告)日：2007-12-13

申请号：US11797034

申请日：2007-04-30

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Naohiko Irie

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Naohiko Irie

IPC分类号： H01L29/73

CPC分类号： G01R31/318572 ,  G11C5/063 ,  G11C11/417 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K3/356008 ,  H03K3/35625 ,  H03K19/0016 ,  H01L2924/00

摘要： In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

摘要翻译： 在功率关闭时保留先前数据的低功耗模式下，其返回速度增加。 虽然可以考虑使用现有的数据保持触发器，但是这不是优选的，因为它增加了诸如扩大单元大小的面积开销。 用于电源关闭的数据保持的电源线由比通常的主电源线更细的布线形成。 优选地，用于数据保持电路的电力线被认为是信号线，并通过自动放置和安装进行布线。 为此，先前通过以与现有信号线相同的方式为小区提供终端来设计用于数据保持的电力线的终端。 电池线的附加布局不再需要，这使得现有的放置和布线工具能够减少面积和设计。

公开(公告)号：US20060146635A1

公开(公告)日：2006-07-06

申请号：US11363060

申请日：2006-02-28

申请人： Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

发明人： Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

IPC分类号： G11C5/14

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G11C5/147 ,  G11C11/417 ,  Y02D10/171

摘要： When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.