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    Semiconductor integrated circuit
    3.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US06798238B2

    公开(公告)日：2004-09-28

    申请号：US10372937

    申请日：2003-02-26

    申请人： Munehito Mushiga ,  Katsuhiro Seta ,  Takeshi Yoshimoto ,  Toshiyuki Furusawa

    发明人： Munehito Mushiga ,  Katsuhiro Seta ,  Takeshi Yoshimoto ,  Toshiyuki Furusawa

    IPC分类号： H03L706

    CPC分类号： H03K19/0016

    摘要： A semiconductor integrated circuit, comprises a first reference voltage line; a second reference voltage line; a plurality of single logic circuits each including a plurality of transistors; a first switch having a first transistor provided between said first reference voltage line and said logic circuits, said first transistor having a higher threshold voltage than that of transistors in the logic circuits; and a second switch having a second transistor provided a between said second transistor having a higher threshold voltage than that of transistors in the logic circuits, said first and second switches being turned on when at least one of said single logic circuits is in operation, while said first and second switches being turned off when all of said single logic circuits are in standby state.

    摘要翻译： 一种半导体集成电路，包括第一参考电压线; 第二参考电压线;多个单个逻辑电路，每个包括多个晶体管; 第一开关，其具有设置在所述第一参考电压线和所述逻辑电路之间的第一晶体管，所述第一晶体管的阈值电压高于逻辑电路中的晶体管; 以及具有第二晶体管的第二开关，所述第二晶体管设置在所述第二晶体管之间，具有比所述逻辑电路中的晶体管更高的阈值电压，所述第一和第二开关在所述单个逻辑电路中的至少一个处于操作时导通，同时 当所有单个逻辑电路都处于待机状态时，所述第一和第二开关断开。

    Cell library for semiconductor integrated circuit design
    4.
    发明授权
    Cell library for semiconductor integrated circuit design 失效
    半导体集成电路设计单元库

    公开(公告)号：US5387810A

    公开(公告)日：1995-02-07

    申请号：US699628

    申请日：1991-05-15

    申请人： Katsuhiro Seta ,  Hiroyuki Hara

    发明人： Katsuhiro Seta ,  Hiroyuki Hara

    IPC分类号： H01L21/82 ,  H01L27/118 ,  H01L29/78 ,  H01L29/73

    CPC分类号： H01L27/11896

    摘要： A cell library for a semiconductor integrated circuit design, comprises a CMOS cell comprising two power source wires and a CMOS circuit placed between the two power source wires at a predetermined distance, and a BiCMOS cell comprising two power source wires which are placed at a distance equal to the distance between the power source wires in the CMOS cell, a CMOS circuit placed between the two power source wires in the BiCMOS cell, and bipolar transistor circuits placed at both outsides of the two power source wires in the BiCMOS cell.

    摘要翻译： 用于半导体集成电路设计的单元库包括CMOS单元，其包括两个电源线和以预定距离放置在两个电源线之间的CMOS电路，以及包括放置在距离处的两个电源线的BiCMOS单元 等于CMOS电池中的电源线之间的距离，放置在BiCMOS单元中的两个电源线之间的CMOS电路，以及放置在BiCMOS单元中的两个电源线的两侧的双极晶体管电路。

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 失效

    公开(公告)号：US5258957A

    公开(公告)日：1993-11-02

    申请号：US849458

    申请日：1992-03-11

    申请人： Katsuhiro Seta ,  Hiroyuki Hara ,  Takayasu Sakurai ,  Yoshinori Watanabe

    发明人： Katsuhiro Seta ,  Hiroyuki Hara ,  Takayasu Sakurai ,  Yoshinori Watanabe

    IPC分类号： G11C11/41 ,  G11C7/06 ,  G11C7/18 ,  G11C11/401 ,  G11C11/414 ,  G11C13/00

    CPC分类号： G11C7/062 ,  G11C7/18

    摘要： In a semiconductor memory device of a divided bit line system, read signals from memory cell blocks are sense-amplified together by a single differential bit line sense amplifier. The bit line sense amplifier includes a plurality of first transistors, the base electrodes of which are connected to local bit lines of the memory cell blocks, the emitter electrodes of which are commonly connected to corresponding main bit lines, and the collector electrodes of which are connected to a first power supply node, a second transistor, which forms a differential pair with each of the first transistors, the base electrode of which is applied with a reference bias potential, and the emitter electrode of which is connected to the main bit lines, a current source connected between the emitter electrode of the second transistor, and a second power supply node, and a load circuit connected between the collector electrode of the second transistor and the first power supply node. The main bit lines with a heavy load can be driven by the emitters having a large driving force, and the outputs from the memory cell blocks can be sensed without going through selectors, thus attaining high-speed read access.

    Cache memory system
    6.
    发明授权
    Cache memory system 失效
    缓存存储系统

    公开(公告)号：US5453947A

    公开(公告)日：1995-09-26

    申请号：US12907

    申请日：1993-02-03

    申请人： Katsuhiro Seta ,  Hiroyuki Hara

    发明人： Katsuhiro Seta ,  Hiroyuki Hara

    IPC分类号： G06F12/08 ,  H01L27/10 ,  G11C15/00

    CPC分类号： G06F12/0895

    摘要： A tag section of a cache memory system comprises a memory for storing a plurality of first address data read out with a small amplitude (e.g., 0.2 Vpp), a circuit for comparing a plurality of second address data, input from the outside of the system, with the plurality of first address data, and providing comparison results with a second amplitude (e.g., 0.8 vpp), an OR logic circuit including a plurality of bipolar transistors having bases to which the comparison results are respectively supplied, collectors connected to a first voltage source, and emitters which are all connected to an emitter dot line, and a circuit for measuring the potential of the emitter dot line by using a reference voltage to determine that all the first and second data coincide with each other. Since a read operation with respect to each tag memory and most hit detecting operations are performed with small-amplitude signals of the ECL level, a high-speed operation can be performed.

    摘要翻译： 高速缓冲存储器系统的标签部分包括用于存储以小幅度（例如，0.2Vpp）读出的多个第一地址数据的存储器，用于比较从系统外部输入的多个第二地址数据的电路 与多个第一地址数据一起提供具有第二幅度（例如，0.8vpp）的比较结果的OR逻辑电路，包括分别提供比较结果的基底的多个双极晶体管的OR逻辑电路，连接到第一 电压源和全部连接到发射体点线的发射极，以及用于通过使用参考电压来测量发射极点线的电位以确定所有第一和第二数据彼此一致的电路。 由于对于每个标签存储器的读取操作和大多数命中检测操作是以ECL电平的小振幅信号执行的，所以可以执行高速操作。

    BiCMOS logic circuit
    7.
    发明授权
    BiCMOS logic circuit 失效
    BiCMOS逻辑电路

    公开(公告)号：US5365124A

    公开(公告)日：1994-11-15

    申请号：US095764

    申请日：1993-07-23

    申请人： Katsuhiro Seta ,  Hiroyuki Hara

    发明人： Katsuhiro Seta ,  Hiroyuki Hara

    IPC分类号： H01L21/8249 ,  H01L27/06 ,  H03K17/567 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/08 ,  H03K19/0944

    CPC分类号： H03K19/0136 ,  H03K19/09448

    摘要： An input terminal IN is connected to the input of a CMOS inverter, and also to the gate of an N-channel MOS transistor N10. The output of the CMOS inverter is coupled to the base of an NPN transistor Q11 used for pulling up the output terminal OUT. The drain of the transistor N10 is connected to the input of a CMOS inverter. The output of the inverter is connected to the base of an NPN transistor Q12 used for pulling down the output terminal OUT. The emitter of the transistor Q11 and the collector of the transistor Q12 are connected to an output terminal OUT, which is coupled to the gate of a P-channel MOS transistor P12 and the gate of an N-channel MOS transistor N3. The drain of the transistor P12 is connected to the drain of the transistor N10. The drain of the transistor N13 is connected to the source of the transistor N10. The transistors N10, P12, and N13 constitute a circuit for controlling the CMOS inverter.

    摘要翻译： 输入端子IN连接到CMOS反相器的输入端，并且连接到N沟道MOS晶体管N10的栅极。 CMOS反相器的输出耦合到用于提升输出端OUT的NPN晶体管Q11的基极。 晶体管N10的漏极连接到CMOS反相器的输入端。 反相器的输出端连接到用于拉出输出端子OUT的NPN晶体管Q12的基极。 晶体管Q11的发射极和晶体管Q12的集电极连接到耦合到P沟道MOS晶体管P12的栅极和N沟道MOS晶体管N3的栅极的输出端子OUT。 晶体管P12的漏极连接到晶体管N10的漏极。 晶体管N13的漏极连接到晶体管N10的源极。 晶体管N10，P12和N13构成用于控制CMOS反相器的电路。

    Barrel shifter device and variable-length decoder
    8.
    发明授权
    Barrel shifter device and variable-length decoder 失效
    桶式移位器和可变长度解码器

    公开(公告)号：US5646873A

    公开(公告)日：1997-07-08

    申请号：US314735

    申请日：1994-09-29

    申请人： Takayoshi Shimazawa ,  Katsuhiro Seta ,  Masataka Matsui

    发明人： Takayoshi Shimazawa ,  Katsuhiro Seta ,  Masataka Matsui

    IPC分类号： G06F7/00 ,  G06F5/01 ,  G06F7/76 ,  H03M7/40

    CPC分类号： G06F5/015

    摘要： A first and second barrel shifters (BSA0 and BSA1) are connected directly without intervening any pipe-line register between the two, and a sense amplifier (R3A0) is provided at an output side of the second barrel register (BSA1). Further, the circuit patterns of the first and second barrel shifters are formed being overlapped with each other in such a way that the elements of one of the first and second barrel shifters are formed at the dead space of the other of the two barrel shifters to reduce the pattern area. In the shift circuit and the variable-length decoder, the data lines of the barrel shifters can be minimized in size and width.

    摘要翻译： 第一和第二桶形移位器（BSA0和BSA1）直接连接，而不插入两者之间的任何管线寄存器，并且在第二桶寄存器（BSA1）的输出侧提供读出放大器（R3A0）。 此外，第一和第二桶形移位器的电路图案被形成为彼此重叠，使得第一和第二桶形移位器中的一个的元件形成在两个桶形移位器中的另一个的死区以至 减少图案面积。 在移位电路和可变长度解码器中，桶形移位器的数据线可以在尺寸和宽度上最小化。