公开(公告)号：US07168073B2

公开(公告)日：2007-01-23

申请号：US10314219

申请日：2002-12-09

申请人： Takashi Asano ,  Nobuki Tominaga

发明人： Takashi Asano ,  Nobuki Tominaga

IPC分类号： G06F9/445 ,  G06F9/44

CPC分类号： G06F8/61 ,  G06F8/62

摘要： A program distribution system capable of discarding a distributed program according to the properties of the program is provided. In the program distribution system, a program is distributed from a program transmission apparatus to a program reception terminal over a network. The program transmission apparatus includes a transmission processing section. The program reception terminal includes a reception-side storage section and a discard processing section. The transmission processing section transmits a program and discarding procedure information to the program reception terminal. The discarding procedure information relates to a procedure of discarding the program performed by the program reception terminal. The reception-side storage section stores the program transmitted from the transmission processing section. The discard processing section discards the program stored in the reception-side storage section according to a discarding procedure specified by the discarding procedure information transmitted from the transmission processing section.

摘要翻译： 提供一种能够根据节目的属性来丢弃分布式节目的节目分发系统。 在节目分配系统中，通过网络从节目发送装置向节目接收终端分发节目。 程序发送装置包括发送处理部。 节目接收终端包括接收侧存储部和丢弃处理部。 发送处理部向节目接收终端发送节目和废弃处理信息。 丢弃过程信息涉及丢弃由节目接收终端执行的节目的过程。 接收侧存储部存储从发送处理部发送的节目。 丢弃处理部根据从发送处理部发送的废弃处理信息指定的废弃处理，丢弃存储在接收侧存储部中的程序。

公开(公告)号：US06647547B1

公开(公告)日：2003-11-11

申请号：US09573487

申请日：2000-05-16

申请人： Tomokazu Kanamaru ,  Nobuki Tominaga ,  Shusuke Haruna

发明人： Tomokazu Kanamaru ,  Nobuki Tominaga ,  Shusuke Haruna

IPC分类号： G06F945

CPC分类号： G06F8/443

摘要： A program conversion apparatus that converts a source program to an executable program, the source program including a first descriptor indicating dynamic memory allocation. The program conversion apparatus includes a specifying unit and a generating unit. The specifying unit specifies in the source program a reference descriptor that is last to be executed from reference descriptors indicating references to memory allocated by the first descriptor. The generating unit generates an instruction for freeing the allocated memory at a position in the executable program immediately following an instruction that corresponds to the specified reference descriptor.

摘要翻译： 一种将源程序转换为可执行程序的程序转换装置，所述源程序包括指示动态存储器分配的第一描述符。 程序转换装置包括指定单元和生成单元。 指定单元在源程序中指定最后从参考描述符执行的参考描述符，该参考描述符指示对由第一描述符分配的存储器的引用。 生成单元生成用于在紧跟在与指定的参照描述符对应的指令之后的可执行程序的位置释放所分配的存储器的指令。

公开(公告)号：US09020241B2

公开(公告)日：2015-04-28

申请号：US13580027

申请日：2012-02-29

申请人： Germano Leichsenring ,  Tomoko Katayama ,  Hidetaka Oto ,  Nobuki Tominaga

发明人： Germano Leichsenring ,  Tomoko Katayama ,  Hidetaka Oto ,  Nobuki Tominaga

IPC分类号： G06K9/00 ,  G06K9/80 ,  G06T19/00 ,  H04N13/00

CPC分类号： G06K9/80 ,  G06T19/00 ,  H04N13/128 ,  H04N13/178

摘要： A image providing device provides a user with realistic and natural past-experience simulation through stereoscopic photographs. Specifically, feature-point extractors extract feature points from a foreground image and a background image, respectively. A stereoscopic matching module searches for pairs of feature points matching between the foreground image and the background image and obtains using the feature point pairs a transformation matrix for projecting the foreground image onto the background image. The transformation by the transformation matrix obtained by the matching unit is applied to foreground depth data, which is depth data of the foreground image. Lastly, depth based rendering is performed based on the transformed foreground depth data to obtain two or more viewpoint images corresponding to the foreground image.

摘要翻译： 图像提供装置通过立体照片为用户提供逼真而自然的过去体验模拟。 具体来说，特征点提取器分别从前景图像和背景图像提取特征点。 立体匹配模块搜索前景图像和背景图像之间匹配的特征点对，并且使用特征点对获得用于将前景图像投影到背景图像上的变换矩阵。 通过由匹配单元获得的变换矩阵的变换被应用于作为前景图像的深度数据的前景深度数据。 最后，基于变换的前景深度数据进行基于深度的渲染，以获得与前景图像相对应的两个或更多个视点图像。

公开(公告)号：US06539433B1

公开(公告)日：2003-03-25

申请号：US09407924

申请日：1999-09-29

申请人： Nobuki Tominaga ,  Shusuke Haruna

发明人： Nobuki Tominaga ,  Shusuke Haruna

IPC分类号： G06F1516

CPC分类号： H04N21/4437 ,  G05B19/042 ,  G05B2219/31156 ,  G05B2219/31161 ,  G05B2219/31186 ,  G05B2219/33121 ,  G05B2219/35008 ,  G06F9/445 ,  H04N21/4131 ,  H04N21/8166 ,  H04N21/8186

摘要： Java bytecode for having home appliances perform a cooperative operation is developed by a development computer and is sent via a communications satellite from the development computer to a TV tuner&home server provided in a home. After the TV tuner&home server receives the Java bytecode, a bytecode converting unit of the TV tuner&home server determines which home appliance is the target appliance of the Java bytecode and converts the Java bytecode into native code for the microprocessor provided in the target appliance. The native code is downloaded into the target appliance via a home appliance network and the target appliance executes the downloaded native code.

摘要翻译： 家用电器执行协作操作的Java字节码由开发计算机开发，并且经由通信卫星从开发计算机发送到家庭中提供的TV调谐器和家庭服务器。 电视调谐器和家庭服务器接收Java字节码后，电视调谐器和家庭服务器的字节码转换单元确定哪个家电是Java字节码的目标设备，并将Java字节码转换为目标设备中提供的微处理器的本地代码。 本地代码通过家用电器网络下载到目标设备中，目标设备执行下载的本机代码。

公开(公告)号：US06425124B1

公开(公告)日：2002-07-23

申请号：US08148887

申请日：1993-11-08

申请人： Nobuki Tominaga ,  Akira Tanaka ,  Seiichi Urushibara

发明人： Nobuki Tominaga ,  Akira Tanaka ,  Seiichi Urushibara

IPC分类号： G06F945

CPC分类号： G06F8/4434 ,  G06F8/4441

摘要： The present invention discloses a resource allocation device comprising a pattern generation unit for generating every pattern of a live variable placing within a program portion subjected to resource allocation and a resource to which the live variable is allocated; an instruction extraction unit for extracting from an instruction storage an instruction sequence corresponding to a combination of an operation placing within the program portion and the resource to which a variable in the operation is allocated, and generating a program comprising the extracted instruction sequences; a cost table for memorizing each instruction sequence and cost thereof which represents the number of execution clocks taken in execution of the instruction sequence; a cost detection unit for detecting the cost of each instruction sequence included in the program from the cost table; a total cost detection unit for summing the cost of each instruction sequence detected by the cost detection unit for each pattern generated by the pattern generation unit; and a best pattern decision unit for deciding the pattern with the lowest cost in all the patterns generated by the pattern generation unit.

摘要翻译： 本发明公开了一种资源分配装置，包括：模式生成部，生成放置在经受资源分配的程序部分内的实时变量的每个模式;分配实时变量的资源; 指令提取单元，用于从指令存储器中提取与放置在所述程序部分内的操作和所述操作中的变量所分配的资源的组合相对应的指令序列，并产生包括所提取的指令序列的程序; 用于存储每个指令序列和成本的代价表，其表示在执行指令序列时执行的执行时钟的数量; 成本检测单元，用于从成本表中检测包括在程序中的每个指令序列的成本; 总成本检测单元，用于对由费用检测单元检测的针对由模式生成单元生成的每个模式的每个指令序列的成本进行求和; 以及最佳图案决定单元，用于以由图案生成单元生成的所有图案中的成本最低的图案来确定图案。

公开(公告)号：US5850551A

公开(公告)日：1998-12-15

申请号：US588051

申请日：1996-01-22

申请人： Shuichi Takayama ,  Nobuo Higaki ,  Nobuki Tominaga ,  Shinya Miyaji

发明人： Shuichi Takayama ,  Nobuo Higaki ,  Nobuki Tominaga ,  Shinya Miyaji

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/45

CPC分类号： G06F9/3804 ,  G06F8/447 ,  G06F9/325

摘要： A compiler comprises a loop detecting unit for extracting information of loops, and a high-speed loop applying unit generating a first loop exclusive instruction, placing the instruction immediately before the entry of a loop, generating second loop exclusive instructions, and placing the instruction at each place to branch to the entry of the loop. A processor comprises: a pipeline comprising: an instruction fetching unit, an instruction decoding unit, and an executing unit; a branch target storage unit; a branch target registering unit for, after the instruction decoding unit has decoded a first loop exclusive instruction, registering branch target information of an instruction succeeding to the first loop exclusive instruction in the branch target registering unit; and a branch executing unit for, after the decoding unit has decoded a second loop exclusive instruction, judging whether to execute a loop, if judges to execute, reading the branch target information registered in the branch target storage unit, and controlling the pipeline so that the program executes the loop using the read branch target information.

摘要翻译： 编译器包括一个用于提取循环信息的循环检测单元和一个生成第一循环专用指令的高速循环应用单元，在循环进入之前立即进行指令，产生第二循环专用指令，并将指令置于 每个地方分支到循环的入口。 一种处理器，包括：流水线，包括：指令获取单元，指令解码单元和执行单元; 分支目标存储单元; 分支目标登记单元，用于在所述指令解码单元解码了第一循环专用指令之后，将在所述分支目标登记单元中的所述第一循环专用指令之后的指令的分支目标信息注册; 以及分支执行单元，用于在解码单元解码了第二循环专用指令之后，判断是否执行循环，如果判断执行，读取登记在分支目标存储单元中的分支目标信息，并且控制流水线，使得 该程序使用读分支目标信息执行循环。

公开(公告)号：US20130071012A1

公开(公告)日：2013-03-21

申请号：US13580027

申请日：2012-02-29

申请人： Germano Leichsenring ,  Tomoko Katayama ,  Hidetaka Oto ,  Nobuki Tominaga

发明人： Germano Leichsenring ,  Tomoko Katayama ,  Hidetaka Oto ,  Nobuki Tominaga

IPC分类号： G06K9/80

CPC分类号： G06K9/80 ,  G06T19/00 ,  H04N13/128 ,  H04N13/178

摘要： A image providing device provides a user with realistic and natural past-experience simulation through stereoscopic photographs. Specifically, feature-point extractors 15 and 22 extract feature points from a foreground image and a background image, respectively. A stereoscopic matching module 25 searches for pairs of feature points matching between the foreground image and the background image and obtains using the feature point pairs a transformation matrix for projecting the foreground image onto the background image. The transformation by the transformation matrix obtained by the matching unit is applied to foreground depth data, which is depth data of the foreground image. Lastly, depth based rendering is performed based on the transformed foreground depth data to obtain two or more viewpoint images corresponding to the foreground image.

摘要翻译： 图像提供装置通过立体照片为用户提供逼真而自然的过去体验模拟。 具体地，特征点提取器15和22分别从前景图像和背景图像提取特征点。 立体匹配模块25搜索前景图像和背景图像之间匹配的特征点对，并且使用特征点对获得用于将前景图像投影到背景图像上的变换矩阵。 通过由匹配单元获得的变换矩阵的变换被应用于作为前景图像的深度数据的前景深度数据。 最后，基于变换的前景深度数据进行基于深度的渲染，以获得与前景图像相对应的两个或更多个视点图像。

公开(公告)号：US5796970A

公开(公告)日：1998-08-18

申请号：US716946

申请日：1996-09-20

申请人： Nobuo Higaki ,  Nobuki Tominaga ,  Shinya Miyaji ,  Shuichi Takayama

发明人： Nobuo Higaki ,  Nobuki Tominaga ,  Shinya Miyaji ,  Shuichi Takayama

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/318 ,  G06F9/34 ,  G06F9/345

CPC分类号： G06F9/30043 ,  G06F9/30138 ,  G06F9/3016

摘要： An information processing apparatus for executing a program, the apparatus including: a register set made up of a plurality of registers; a decoding unit for decoding machine language instructions in the program and extracting a selected instruction which indicates data transfer between a plurality of registers designated by a first operand, which is made up of a single field of at least one bit which shows whether an individual register out of the register set is designated and a group field which shows whether a plurality of other registers out of the register set are designated as a group, and consecutive addresses of memory designated by a second operand as an effective address of memory; a determining unit for determining whether each bit in the single field and group field of the first operand of the extracted machine language instruction is valid; a first generating unit for generating a register number for a register corresponding to a bit determined as being valid in the single field, a second generating unit for generating in order a register number of each register to which the group field relates, when a bit in the group field has been determined as being valid; and a transferring unit for executing data transfer between the registers identified by the register numbers generated by the first generating unit and the second generating unit and the consecutive memory areas starting from the effective address.

摘要翻译： 一种用于执行程序的信息处理装置，所述装置包括：由多个寄存器组成的寄存器组; 解码单元，用于对程序中的机器语言指令进行解码，并提取指示由第一操作数指定的多个寄存器之间的数据传送的选择指令，该第一操作数由至少一位的单个字段组成，其显示单个寄存器 指定寄存器组中的多个其他寄存器被指定为组，并且将由第二操作数指定的存储器的连续地址指定为存储器的有效地址的组字段; 确定单元，用于确定所提取的机器语言指令的第一操作数的单个字段和组字段中的每个位是否有效; 第一生成单元，用于生成对应于在单个字段中被确定为有效的比特的寄存器的寄存器号;第二生成单元，用于按顺序生成与组域相关的每个寄存器的寄存器号， 组合领域已被确定为有效; 以及传送单元，用于执行由由第一生成单元和第二生成单元生成的寄存器号码识别的寄存器和从有效地址开始的连续存储区域之间的数据传送。

公开(公告)号：US20120147042A1

公开(公告)日：2012-06-14

申请号：US13391828

申请日：2011-06-21

申请人： Yuki Shinomoto ,  Hidehiko Shin ,  Tomoko Katayama ,  Nobuki Tominaga

发明人： Yuki Shinomoto ,  Hidehiko Shin ,  Tomoko Katayama ,  Nobuki Tominaga

IPC分类号： G09G5/377

CPC分类号： G02B27/017 ,  G02B2027/014 ,  G06T11/60 ,  G09G5/12 ,  G09G2340/12 ,  G09G2340/14 ,  G09G2360/121 ,  G09G2370/027 ,  G09G2380/02 ,  G09G2380/14

摘要： An electronic publication viewer (1000) includes a display target specifying unit (1100) that specifies a display target page and the position and size of the display target region, a page structure data obtaining unit (1200) that obtains page structure data corresponding to the display target page, a rendering unit (1300) that generates the display image data corresponding to the position and size of the display target region, a display image data caching unit (1400) that caches the display image data, and a display control unit (1500) that causes the display image data obtained from the rendering unit (1300) or the display image data caching unit (1400) in a position of a display unit superimposed on the display target region.

摘要翻译： 电子出版物浏览器（1000）包括指定显示目标页面的显示目标指定单元（1100）和显示目标区域的位置和大小，页面结构数据获取单元（1200），其获得与 显示目标页面，生成与显示目标区域的位置和大小相对应的显示图像数据的绘制单元（1300），高速缓存显示图像数据的显示图像数据高速缓存单元（1400），以及显示控制单元 1500），其将从渲染单元（1300）或显示图像数据高速缓存单元（1400）获得的显示图像数据置于叠加在显示目标区域上的显示单元的位置。

公开(公告)号：US06170998B2

公开(公告)日：2001-01-09

申请号：US08589854

申请日：1996-01-22

申请人： Kazushi Yamamoto ,  Shuichi Takayama ,  Nobuo Higaki ,  Nobuki Tominaga ,  Shinya Miyaji

发明人： Kazushi Yamamoto ,  Shuichi Takayama ,  Nobuo Higaki ,  Nobuki Tominaga ,  Shinya Miyaji

IPC分类号： G06F945

CPC分类号： G06F9/3806 ,  G06F8/447 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/4486

摘要： A processor detects a function which includes no function call instruction and no update of the return address /calculation register from an assembler program. After the detection, the processor outputs a special return address to the end of the function detected, and executes the assembler program. The processor stores a return address not only on the stack but in the return address/calculation register. When the special return instruction has been fetched, the return address is moved from the return address/calculation register without accessing to the stack.

摘要翻译： 处理器检测到一个不包含函数调用指令的函数，并且没有从汇编程序更新返回地址/计算寄存器。 检测完毕后，处理器输出特殊的返回地址到检测到的功能结束，并执行汇编程序。 处理器不仅在堆栈中存储返回地址，而且在返回地址/计算寄存器中存储。 当获取特殊的返回指令时，返回地址从返回地址/计算寄存器移动，而不访问堆栈。