Energy saving multiplication device and method
    1.
    发明授权
    Energy saving multiplication device and method 有权
    节能倍增装置及方法

    公开(公告)号:US06785702B2

    公开(公告)日:2004-08-31

    申请号:US09861572

    申请日:2001-05-22

    CPC classification number: G06F7/49942 G06F7/52

    Abstract: An energy saving multiplication device and its method is disclosed. The multiplication device includes a dynamic range determination unit, a Booth encoding/decoding unit and a counter array. The dynamic range determination unit determines dynamic ranges of the numerical values to be multiplied together and outputs after processing according to the dynamic-range size relation of the input data. The Booth encoding/decoding unit couples to the dynamic range determination unit. The counter array couples to the Booth encoding/decoding unit for accumulating the partial products to obtain the products of the input data.

    Abstract translation: 公开了一种节能倍增装置及其方法。 乘法装置包括动态范围确定单元,布尔编码/解码单元和计数器阵列。 动态范围确定单元确定要相乘的数值的动态范围,并根据输入数据的动态范围大小关系在处理之后输出。 展位编码/解码单元耦合到动态范围确定单元。 计数器阵列耦合到布斯编码/解码单元,用于累积部分乘积以获得输入数据的乘积。

    Apparatus of high dynamic-range CMOS image sensor and method thereof

    公开(公告)号:US20090002533A1

    公开(公告)日:2009-01-01

    申请号:US12149973

    申请日:2008-05-12

    CPC classification number: H04N5/374 H01L27/14609 H04N5/35518

    Abstract: The present invention discloses an apparatus of high dynamic-range CMOS image sensor and method thereof. The present invention utilize a pixel circuit outputting an output signal, wherein the pixel circuit has a photodiode and a plurality of transistors; and utilize a current source as a charge supplement unit to supply current into one end of the photodiode, and providing charges to the parasitic capacitor of the photodiode to delay saturation in the pixel circuit. In addition, a feedback circuit can be further designed connecting the pixel circuit. The feedback circuit receives the output signal from the pixel circuit and then outputs a control signal according to the output signal of the pixel circuit to control status of the charge supplement unit, and thereby increasing the dynamic range of the CMOS image sensor.

    Method of automatically determining the region of interest from an image
    3.
    发明授权
    Method of automatically determining the region of interest from an image 失效
    从图像自动确定感兴趣区域的方法

    公开(公告)号:US07162095B2

    公开(公告)日:2007-01-09

    申请号:US10460362

    申请日:2003-06-13

    Abstract: A method for automatically determining the region of interest from an image comprises the three steps of (a) analyzing content of the transformed coefficients of an image after a discrete signal transformation and partitioning an image into the interested region and background region that are based on p×p-pixel sub-blocks for performing classification; (b) locating the central point of the interested sub-blocks; and (c) integrating a plurality of the interested sub-blocks from said central point to the boundary of an image to generate a closed and continued region of interest by using a image processing technique with considering the bit-rate requirement.

    Abstract translation: 一种用于从图像自动确定感兴趣区域的方法包括以下三个步骤:(a)分析离散信号变换之后的图像的变换系数的内容,并将图像分割成基于pxp的感兴趣区域和背景区域 用于执行分类的子像素块; (b)定位感兴趣的子块的中心点; 以及(c)通过使用考虑到比特率要求的图像处理技术,将多个感兴趣的子块从所述中心点整合到图像的边界以产生关闭和继续的感兴趣区域。

    Arithmetic device and method with low power consumption
    5.
    发明授权
    Arithmetic device and method with low power consumption 有权
    具有低功耗的算术装置和方法

    公开(公告)号:US06629119B1

    公开(公告)日:2003-09-30

    申请号:US09452219

    申请日:1999-12-01

    CPC classification number: G06F7/57 G06F2207/3816

    Abstract: An arithmetic device with low power consumption includes master latches, a dynamic range detection unit, slave latches, an operation unit, and a word-length restoration unit. In the arithmetic device, the master latches latch a plurality of (such as two) input data. The dynamic range detection unit detects the effective dynamic range of these input data. The slave latches latch the values of the effective dynamic-range bits of these input data. The operation unit performs predetermined operations of the bits of these effective dynamic range to obtaing an operation result. Since the operation unit only performs operations of the bits of the effective dynamic range, the circuit corresponding to other bits will not demonstrate switching of power consumption, thereby lowering the overall power consumption. Furthermore, the word-length restoration unit will complement the operation result to its original output length in association with the sign of the operation result, for obtaining the correct operation result.

    Abstract translation: 具有低功耗的算术装置包括主锁存器,动态范围检测单元,从锁存器,操作单元和字长恢复单元。 在算术装置中,主锁存器锁存多个(如两个)输入数据。 动态范围检测单元检测这些输入数据的有效动态范围。 从锁存器锁存这些输入数据的有效动态范围位的值。 操作单元执行这些有效动态范围的位的预定操作以获得操作结果。 由于操作单元仅执行有效动态范围的位的操作,所以对应于其他位的电路将不会显示功耗的切换,从而降低总功耗。 此外,字长恢复单元将与操作结果的符号相关联的操作结果与其原始输出长度相匹配,以获得正确的操作结果。

    Programmable finite impulse response processor with scalable dynamic
data range
    6.
    发明授权
    Programmable finite impulse response processor with scalable dynamic data range 失效
    可编程有限脉冲响应处理器,具有可扩展的动态数据范围

    公开(公告)号:US6163788A

    公开(公告)日:2000-12-19

    申请号:US104341

    申请日:1998-06-25

    CPC classification number: G06F17/10

    Abstract: A programmable finite impulse response processor, by which a convolution calculation between input data and filter coefficients is performed based on Booth algorithm. The processor include a pre-processing unit, data latches, a configurable connection unit, Booth decoders, coefficient registers, a path control unit, and a post-processing unit. The pre-processing unit is used to partition the input data into a pipeline sequence which include a plurality of sequence units in a Booth format. According to both the dynamic ranges of the input data and of the filter coefficients, the configurable connection unit is used to select certain parts of the sequence units for the convolution calculation, so that a dynamic data range is scaleable by the processor. By Booth decoders, the selected sequence units are decoded and multiplied by corresponding filter coefficients stored in the coefficient registers. By the path control unit, the bit lengths of the filter coefficients are scaled and accumulation pathes are selected. The post-processing unit is to perform a final accumulation of the convolution calculation results between the selected sequence units and the filter coefficients.

    Abstract translation: 一种可编程有限脉冲响应处理器,通过该方法,基于Booth算法进行输入数据和滤波器系数之间的卷积计算。 处理器包括预处理单元,数据锁存器,可配置连接单元,布尔解码器,系数寄存器,路径控制单元和后处理单元。 预处理单元用于将输入数据划分成包括布列斯格式的多个序列单元的流水线序列。 根据输入数据和滤波器系数的动态范围,可配置连接单元用于选择用于卷积计算的序列单元的某些部分,使得动态数据范围可由处理器缩放。 通过布斯解码器,所选择的序列单元被解码并乘以存储在系数寄存器中的对应的滤波器系数。 通过路径控制单元,对滤波器系数的比特长度进行缩放,并选择累积斑纹。 后处理单元是在所选序列单元和滤波器系数之间执行卷积计算结果的最终累积。

    Apparatus of high dynamic-range CMOS image sensor and method thereof
    7.
    发明授权
    Apparatus of high dynamic-range CMOS image sensor and method thereof 失效
    高动态范围CMOS图像传感器的设备及其方法

    公开(公告)号:US07605398B2

    公开(公告)日:2009-10-20

    申请号:US11211670

    申请日:2005-08-26

    CPC classification number: H04N5/374 H01L27/14609 H04N5/35518

    Abstract: The present invention discloses an apparatus of high dynamic-range CMOS image sensor and method thereof. The present invention utilize a pixel circuit outputting an output signal, wherein the pixel circuit has a photodiode and a plurality of transistors; and utilize a current source as a charge supplement unit to supply current into one end of the photodiode, and providing charges to the parasitic capacitor of the photodiode to delay saturation in the pixel circuit. In addition, a feedback circuit can be further designed connecting the pixel circuit. The feedback circuit receives the output signal from the pixel circuit and then outputs a control signal according to the output signal of the pixel circuit to control status of the charge supplement unit, and thereby increasing the dynamic range of the CMOS image sensor.

    Abstract translation: 本发明公开了一种高动态范围CMOS图像传感器及其方法。 本发明利用输出输出信号的像素电路,其中像素电路具有光电二极管和多个晶体管; 并且利用电流源作为电荷补充单元来向光电二极管的一端提供电流,并向光电二极管的寄生电容器提供电荷以延迟像素电路中的饱和。 此外,可以进一步设计连接像素电路的反馈电路。 反馈电路从像素电路接收输出信号,然后根据像素电路的输出信号输出控制信号,控制电荷补充单元的状态,从而增加CMOS图像传感器的动态范围。

    Motion vector prediction method and prediction apparatus thereof
    8.
    发明申请
    Motion vector prediction method and prediction apparatus thereof 审中-公开
    运动矢量预测方法及其预测装置

    公开(公告)号:US20080159402A1

    公开(公告)日:2008-07-03

    申请号:US12000985

    申请日:2007-12-19

    CPC classification number: H04N19/423 H04N19/52 H04N19/61

    Abstract: A motion vector (MV) prediction method and a prediction apparatus thereof are applicable for a video image encoder/decoder to predict an MV of a video image. Firstly, segment a macroblock in the video image into microblocks. Then, configure a row memory and three register memories to register the MV required for prediction. Finally, the MV stored in the row memory or the register memories at a position corresponding to the current microblock to be predicted is used to predict the MV of the current microblock to be predicted in the current macroblock to be predicted. After the prediction is completed and moved to another macroblock or microblock, the MV stored in the row memory or the register memories is updated according to a predetermined storage updating condition.

    Abstract translation: 运动矢量(MV)预测方法及其预测装置可应用于视频图像编码器/解码器来预测视频图像的MV。 首先,将视频图像中的宏块分割为微块。 然后,配置行存储器和三个寄存器存储器来注册预测所需的MV。 最后,将存储在行存储器中的MV或与要预测的当前微块对应的位置的寄存器存储器用于预测要预测的当前宏块中要预测的当前微块的MV。 在预测完成并移动到另一个宏块或微块之后,根据预定的存储更新条件更新存储在行存储器或寄存器存储器中的MV。

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