公开(公告)号：US09098302B2

公开(公告)日：2015-08-04

申请号：US13536449

申请日：2012-06-28

Applicant: Robert Swanson ,  Mallik Bulusu ,  Palsamy Sakthikumar ,  Ramamurthy Krithivas ,  James Steven Burns

Inventor： Robert Swanson ,  Mallik Bulusu ,  Palsamy Sakthikumar ,  Ramamurthy Krithivas ,  James Steven Burns

IPC: G06F9/00 ,  G06F9/44

CPC classification number: G06F9/4406 ,  G06F9/4401

Abstract: Methods and apparatus are disclosed to improve system boot speed. A disclosed example method includes associating a first serial peripheral interface (SPI) with a baseboard management controller (BMC), copying an image from the first SPI to a volatile memory in response to receiving power at the BMC, and in response to receiving an access request associated with the first SPI, providing access to the image stored in the volatile memory.

Abstract translation: 公开了提高系统引导速度的方法和装置。 所公开的示例性方法包括将第一串行外设接口（SPI）与基板管理控制器（BMC）相关联，响应于BMC处的接收功率将图像从第一SPI复制到易失性存储器，以及响应于接收到访问 请求与第一SPI相关联，提供对存储在易失性存储器中的图像的访问。

公开(公告)号：US20140089573A1

公开(公告)日：2014-03-27

申请号：US13625673

申请日：2012-09-24

Applicant: Palsamy Sakthikumar ,  Eswaramoorthi Nallusamy ,  Rahul Khanna ,  Kuljit S. Bains

Inventor： Palsamy Sakthikumar ,  Eswaramoorthi Nallusamy ,  Rahul Khanna ,  Kuljit S. Bains

IPC: G06F12/00

CPC classification number: G06F13/1689

Abstract: Embodiments of the invention describe apparatuses, systems and methods for enabling memory device access prior to bus training, thereby enabling firmware image storage in non-flash nonvolatile memory, such as DDR DRAM. The increasing size of firmware images, such as BIOS, MRC, and ME firmware, makes current non-volatile storage solutions, such as SPI flash memory, impractical; executing BIOS code in flash is slow, and having a separate non-volatile memory device increases device costs. Furthermore, solutions such as Cache-as-RAM, which are utilized for running the pre-memory BIOS code, are limited by the cache size that is not scalable to the increasing complexity of BIOS code.Embodiments of the invention enable the use of persistent memory, such as DRAM, for BIOS code execution and data transfer by allowing DRAM access before memory channel training; said firmware images may then executed to “train” memory channels for subsequent system use.

Abstract translation: 本发明的实施例描述了用于在总线训练之前使存储器件访问的装置，系统和方法，从而使得非易失性存储器（例如DDR DRAM）中的固件图像存储能够实现。 诸如BIOS，MRC和ME固件等固件映像的增加使当前的非易失性存储解决方案（如SPI闪存）变得不切实际; 在闪存中执行BIOS代码很慢，并且具有单独的非易失性存储器设备会增加设备成本。 此外，用于运行预存储器BIOS代码的诸如Cache-as-RAM的解决方案受到不能随着BIOS代码日益增加的复杂性而变化的高速缓存大小的限制。 本发明的实施例能够通过在存储器信道训练之前​​允许DRAM访问来使用诸如DRAM之类的持久存储器用于BIOS代码执行和数据传输; 所述固件图像然后可以被执行以“训练”存储器通道用于随后的系统使用。

公开(公告)号：US20140089551A1

公开(公告)日：2014-03-27

申请号：US13627512

申请日：2012-09-26

Applicant: David C. Estrada ,  Vincent J. Zimmer ,  Palsamy Sakthikumar

Inventor： David C. Estrada ,  Vincent J. Zimmer ,  Palsamy Sakthikumar

IPC: G06F13/40

CPC classification number: G06F9/4411 ,  G06F9/4406 ,  G06F13/26 ,  G06F13/4027

Abstract: Various embodiments are directed to creating multiple device blocks associated with hardware devices, arranging the device blocks in an order indicative of positions of the hardware devices in a hierarchy of buses and bridges, and enabling access to the multiple device blocks from an operating system. An apparatus comprises a processor circuit and storage storing instructions operative on the processor circuit to create a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices accessible to the processor circuit, the device blocks arranged in an order indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device; enable access to the device table by an operating system; and execute a second sequence of instructions of the operating system operative on the processor circuit to access the device table. Other embodiments are described and claimed herein.

Abstract translation: 各种实施例涉及创建与硬件设备相关联的多个设备块，以指示总线和桥接器层级中的硬件设备的位置的顺序排列设备块，以及使得能够从操作系统访问多个设备块。 一种装置包括处理器电路和存储器，其存储指令，其操作在所述处理器电路上以创建包括多个设备块的设备表，每个设备块对应于所述处理器电路可访问的多个硬件设备之一，所述设备块以指示 硬件设备在总线和至少一个桥接设备层级中的相对位置; 使操作系统能够访问设备表; 并且执行在处理器电路上操作的操作系统的第二指令序列以访问设备表。 在此描述和要求保护的其它实施例。

公开(公告)号：US20140047174A1

公开(公告)日：2014-02-13

申请号：US13570315

申请日：2012-08-09

Applicant: Palsamy Sakthikumar ,  Vincent J. Zimmer ,  Robert C. Swanson ,  Eswaramoorthi Nallusamy

Inventor： Palsamy Sakthikumar ,  Vincent J. Zimmer ,  Robert C. Swanson ,  Eswaramoorthi Nallusamy

IPC: G06F12/14

CPC classification number: G06F12/1416 ,  G06F12/1425

Abstract: Generally, this disclosure provides methods and systems for secure data protection with improved read-only memory locking during system pre-boot including protection of Advanced Configuration and Power Interface (ACPI) tables. The methods may include selecting a region of system memory to be protected, the selection occurring in response to a system reset state and performed by a trusted control block (TCB) comprising a trusted basic input/output system (BIOS); programming an address decoder circuit to configure the selected region as read-write; moving data to be secured to the selected region; programming the address decoder circuit to configure the selected region as read-only; and locking the read-only configuration in the address decoder circuit.

Abstract translation: 通常，本公开提供用于在系统预引导期间具有改进的只读存储器锁定的安全数据保护的方法和系统，包括高级配置和电源接口（ACPI）表的保护。 所述方法可以包括选择要保护的系统存储器的区域，响应于系统复位状态而发生的选择并且由包括可信赖的基本输入/输出系统（BIOS）的信任控制块（TCB）执行的选择; 编程地址解码器电路以将所选择的区域配置为读写; 将数据移动到所选区域; 编程地址解码器电路将所选区域配置为只读; 并将只读配置锁定在地址解码器电路中。

公开(公告)号：US20110314298A1

公开(公告)日：2011-12-22

申请号：US12819933

申请日：2010-06-21

Applicant: Vincent J. Zimmer ,  Michael A. Rothman ,  Robert C. Swanson ,  Palsamy Sakthikumar ,  Mallik Bulusu

Inventor： Vincent J. Zimmer ,  Michael A. Rothman ,  Robert C. Swanson ,  Palsamy Sakthikumar ,  Mallik Bulusu

IPC: G06F21/00

CPC classification number: G06F21/57 ,  G06F2221/2111 ,  G06F2221/2151

Abstract: Enhancing locality in a security co-processor module of a computing system may be achieved by including one or more additional attributes such as geographic location, trusted time, a hardware vendor string, and one or more environmental factors into an access control space for machine mode measurement of a computing system.

Abstract translation: 可以通过将一个或多个附加属性（诸如地理位置，可信时间，硬件供应商串和一个或多个环境因素）包括在用于机器模式的访问控制空间中来实现计算系统的安全协处理器模块中的局部性 计算系统的测量。

公开(公告)号：US20090023414A1

公开(公告)日：2009-01-22

申请号：US11779803

申请日：2007-07-18

Applicant: Vincent J. Zimmer ,  Michael A. Rothman ,  Palsamy Sakthikumar ,  Mallik Bulusu ,  Robert C. Swanson

Inventor： Vincent J. Zimmer ,  Michael A. Rothman ,  Palsamy Sakthikumar ,  Mallik Bulusu ,  Robert C. Swanson

IPC: H04B1/26

CPC classification number: H04W88/06 ,  G06F9/5077

Abstract: A software-defined radio (SDR) capability may be provided in a general purpose, many core processing system by sequestering one or more partitions running on one or more cores and instantiating a communications capability by having discrete SDR functions performed by the sequestered partitions. Each SDR module embodied in a sequestered partition may be independently upgraded without modifying the hardware of the underlying processing system. By executing SDR modules in cores not accessible by application programs and/or an operating system (OS), a better Quality of Service (QoS) may be provided for wireless communications on the general purpose, multi-core processing system. An embodiment comprises isolating a core of a many core processing system as a sequestered partition, loading a software-defined radio module onto the core, and executing the software-defined module to implement wireless communications.

Abstract translation: 可以在通用目的的许多核心处理系统中通过隔离在一个或多个核上运行的一个或多个分区并通过具有由隔离分区执行的离散SDR功能来实例化通信能力来提供软件定义无线电（SDR）能力。 实施在隔离分区中的每个SDR模块可以独立升级，而无需修改底层处理系统的硬件。 通过在应用程序和/或操作系统（OS）不可访问的核心中执行SDR模块，可以为通用多核处理系统上的无线通信提供更好的服务质量（QoS）。 一个实施例包括将许多核心处理系统的核心隔离为隔离分区，将软件定义的无线电模块加载到核心上，以及执行软件定义模块以实现无线通信。

公开(公告)号：US08402262B2

公开(公告)日：2013-03-19

申请号：US12966607

申请日：2010-12-13

Applicant: Palsamy Sakthikumar ,  Vincent J. Zimmer

Inventor： Palsamy Sakthikumar ,  Vincent J. Zimmer

IPC: G06F9/00 ,  G06F9/24 ,  G06F1/00

CPC classification number: G06F9/4405

Abstract: In one embodiment, the present invention includes a method for receiving a request for power-up of a first blade of a chassis, enabling the first blade to power-up in a reduced boot mode and receiving a communication including characteristic information and policy information associated with the first blade, and analyzing the characteristic information and the policy information to determine a policy and a boot configuration for the first blade. Other embodiments are described and claimed.

公开(公告)号：US20120079306A1

公开(公告)日：2012-03-29

申请号：US12890222

申请日：2010-09-24

Applicant: Sarathy Jayakumar ,  Gopal R. Mundada ,  Palsamy Sakthikumar

Inventor： Sarathy Jayakumar ,  Gopal R. Mundada ,  Palsamy Sakthikumar

IPC: G06F11/30 ,  G06F13/20

CPC classification number: G06F11/3062 ,  G06F11/3031 ,  G06F11/3037 ,  G06F11/327

Abstract: Memory reconfiguration during system run-time is described. In one example, a system includes a memory slot to carry a memory board and to connect the memory board to a memory controller for read and write operations, a logic device having a plurality of status registers to record the status of the memory slot and a plurality of control registers to control the operation of the memory slot, and a bus interface coupled through direct signal lines to the memory slot to communicate status and control signals with the memory slot and coupled through a serial bus to the logic device to communicate status and control signals with the logic device.

Abstract translation: 描述系统运行时的内存重新配置。 在一个示例中，系统包括用于承载存储器板并且将存储器板连接到存储器控制器用于读取和写入操作的存储器插槽，具有多个状态寄存器以记录存储器槽的状态的逻辑设备和 多个控制寄存器来控制存储器插槽的操作，以及总线接口，通过直接信号线耦合到存储器插槽，以与存储器槽通信状态和控制信号，并通过串行总线耦合到逻辑器件以传送状态和 控制信号与逻辑器件。

公开(公告)号：US20120025953A1

公开(公告)日：2012-02-02

申请号：US12848654

申请日：2010-08-02

Applicant: Robert C. Swanson ,  Vincent J. Zimmer ,  Mallik Bulusu ,  Michael A. Rothman ,  Palsamy Sakthikumar

Inventor： Robert C. Swanson ,  Vincent J. Zimmer ,  Mallik Bulusu ,  Michael A. Rothman ,  Palsamy Sakthikumar

IPC: G06K7/01

CPC classification number: H04L45/02 ,  H04W4/80 ,  H04W84/18

Abstract: Using radio frequency identification (RFID) tags embedded in processors within a computing system to assist in system initialization processing. The RFID tags provide a separate communication path to other components of the computing system during initialization processing, apart from the system interconnect. When the computing system is powered up, each processor in the system may cause its RFID tag to broadcast data regarding the processor's interconnect location and initialization status. The RFID tags may be sensed by a RFID receiver in the Platform Control Hub (PCH) of the computing system, and each processor's interconnect location and initialization status data may be stored in selected registers within the PCH. When the BIOS executes during system initialization processing, the BIOS may access these PCH registers to obtain the processor's data. The interconnect location and initialization status data may be used by the BIOS to select the optimal routing table and to configure the virtual network within the computing system based at least in part on the optimal routing table and the RFID tag data and without the need for interrogating each processor individually over the system interconnect.

Abstract translation: 使用嵌入在计算系统内的处理器中的射频识别（RFID）标签来协助系统初始化处理。 除了系统互连，RFID标签在初始化处理期间提供到计算系统的其他组件的单独的通信路径。 当计算系统通电时，系统中的每个处理器可能使其RFID标签广播关于处理器的互连位置和初始化状态的数据。 RFID标签可以由计算系统的平台控制中心（PCH）中的RFID接收器感测，并且每个处理器的互连位置和初始化状态数据可以存储在PCH内的选定的寄存器中。 当BIOS在系统初始化处理期间执行时，BIOS可以访问这些PCH寄存器以获得处理器的数据。 BIOS可以使用互连位置和初始化状态数据来选择最佳路由表并且至少部分地基于最佳路由表和RFID标签数据来配置计算系统内的虚拟网络，并且不需要询问 每个处理器分别通过系统互连。

公开(公告)号：US20110307712A1

公开(公告)日：2011-12-15

申请号：US12814246

申请日：2010-06-11

Applicant: Palsamy Sakthikumar ,  Robert C. Swanson ,  Vincent J. Zimmer ,  Michael A. Rothman ,  Mallik Bulusu

Inventor： Palsamy Sakthikumar ,  Robert C. Swanson ,  Vincent J. Zimmer ,  Michael A. Rothman ,  Mallik Bulusu

IPC: H04L9/00

CPC classification number: G06F21/572 ,  G06F2221/2141

Abstract: A method, apparatus, system, and computer program product for multi-owner deployment of firmware images. The method includes obtaining a signed firmware image that comprises a first code module signed by a first code owner and a second code module signed by a second code owner. The method further includes obtaining an updated first code module comprising updated code for the first code module, verifying that the updated first code module is signed by the first code owner, and updating the signed firmware image with the updated first code module in response to verifying that the updated first code module is signed by the first code owner. The signed firmware image may further comprise an access control list that authorizes updates to the first code module by the first code owner and updates to the second code module by the second code owner.

Abstract translation: 一种用于多所有者部署固件映像的方法，设备，系统和计算机程序产品。 该方法包括获得包括由第一代码所有者签名的第一代码模块和由第二代码所有者签名的第二代码模块的签名固件映像。 所述方法还包括获得包括用于第一代码模块的更新代码的更新的第一代码模块，验证所更新的第一代码模块是否被第一代码所有者签名，以及响应于验证更新带有更新的第一代码模块的已签名固件映像 更新的第一代码模块由第一代码所有者签名。 签名的固件图像还可以包括访问控制列表，其授权第一代码所有者更新第一代码模块，并由第二代码所有者更新第二代码模块。