公开(公告)号：US20090075698A1

公开(公告)日：2009-03-19

申请号：US11855846

申请日：2007-09-14

申请人： Zhimin Ding ,  Richard M. Morley ,  Stephen Johnston ,  Bing Yeh ,  John E. Berg

发明人： Zhimin Ding ,  Richard M. Morley ,  Stephen Johnston ,  Bing Yeh ,  John E. Berg

IPC分类号： H04B1/38

CPC分类号： H04W8/245 ,  H04W48/08 ,  H04W48/18 ,  H04W88/06

摘要： A removable card for use with a mobile wireless communication device has a processor and a non-volatile memory, connected to the processor. The memory has programming code stored configured to be executed by the processor and is operable in one of two modes. In a first mode the card is connected to the device with the card storing information received wirelessly by the device from the Internet. In a second mode the card is connected to a network portal device, which is connected to the Internet, with the card storing information received through the network portal device from the Internet. In another embodiment, the removable card has electrical connections for connecting to a mobile wireless communicating device for use by a user to connect to the Internet. The memory has two portions: a first portion and a second portion with the partitioning being alterable. The processor restricts access to the first portion by the user, while grants access to the second portion to the user. Finally, the present invention relates to a mobile wireless communication device.

摘要翻译： 用于移动无线通信设备的可拆卸卡具有连接到处理器的处理器和非易失性存储器。 存储器具有被配置为由处理器执行并且可以以两种模式之一操作的存储的编程代码。 在第一模式中，卡被连接到设备，其中卡存储由设备从因特网无线地接收到的信息。 在第二模式中，该卡连接到连接到互联网的网络入口设备，其中卡从存储通过网络入口设备从因特网接收的信息。 在另一个实施例中，可拆卸卡具有用于连接到移动无线通信设备的电连接，供用户使用以连接到因特网。 存储器具有两部分：第一部分和第二部分，其中分割是可改变的。 处理器限制用户对第一部分的访问，同时向用户授予对第二部分的访问。 最后，本发明涉及移动无线通信设备。

公开(公告)号：US20140329244A1

公开(公告)日：2014-11-06

申请号：US14128486

申请日：2012-06-25

申请人： Zhimin Ding ,  Fang Wu ,  Li Liu

发明人： Zhimin Ding ,  Fang Wu ,  Li Liu

IPC分类号： C12Q1/68

CPC分类号： C12Q1/6806 ,  B01L7/52 ,  B01L2200/028 ,  B01L2200/147 ,  B01L2200/148 ,  B01L2200/16 ,  B01L2300/043 ,  B01L2300/0654 ,  B01L2300/1822 ,  B01L2300/1827

摘要： Described herein is a chip-based apparatus for amplifying nucleic acids, a cartridge housing the apparatus, and methods of using the apparatus for amplification of nucleic acids. More specifically, this invention provides integrated semiconductor chip, manufactured with standard semiconductor manufacturing process, with on-chip circuitry to perform thermal management and optical sensing necessary for amplification of nucleic acids. The apparatus and methods embodied in this invention makes it possible to build a disease diagnosis and prognosis tool that is easy to use, portable and disposable.

摘要翻译： 本文描述了用于扩增核酸的基于芯片的装置，容纳该装置的盒和使用用于扩增核酸的装置的方法。 更具体地，本发明提供了具有标准半导体制造工艺制造的集成半导体芯片，具有片上电路以执行核酸扩增所需的热管理和光学感测。 本发明实施的装置和方法使得构建易于使用，便携和一次性的疾病诊断和预后工具成为可能。

公开(公告)号：US08392641B2

公开(公告)日：2013-03-05

申请号：US12785943

申请日：2010-05-24

申请人： Pankaj Shrivastava ,  Gregory Goodhue ,  Ata Khan ,  Zhimin Ding ,  Craig MacKenna

发明人： Pankaj Shrivastava ,  Gregory Goodhue ,  Ata Khan ,  Zhimin Ding ,  Craig MacKenna

IPC分类号： G06F13/24

CPC分类号： G06F9/4812 ,  G06F9/462 ,  G06F13/26 ,  Y02D10/14 ,  Y02D10/24

摘要： Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.

摘要翻译： 本公开的方面涉及具有特别配置的微控制器的系统。 在一个实施例中，微控制器包括以下：处理器; 连接到处理器的处理器数据总线; 一套外设; 连接到外围设备的外围数据总线; 提供处理器数据总线和外围数据库之间的接口的外围总线桥，并且包括微控制器内部的多个特殊功能寄存器组块，每个寄存器组块具有相应的输出; 以及寄存器块解码器电路，用于解码中断以提供用于激活所述多个寄存器组块之一的选择输出。

公开(公告)号：US20100299471A1

公开(公告)日：2010-11-25

申请号：US12785943

申请日：2010-05-24

申请人： Pankaj Shrivastava ,  Gregory Goodhue ,  Ata khan ,  Zhimin Ding ,  Craig Mackenna

发明人： Pankaj Shrivastava ,  Gregory Goodhue ,  Ata khan ,  Zhimin Ding ,  Craig Mackenna

IPC分类号： G06F13/24

CPC分类号： G06F9/4812 ,  G06F9/462 ,  G06F13/26 ,  Y02D10/14 ,  Y02D10/24

摘要： Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.

摘要翻译： 本公开的方面涉及具有特别配置的微控制器的系统。 在一个实施例中，微控制器包括以下：处理器; 连接到处理器的处理器数据总线; 一套外设; 连接到外围设备的外围数据总线; 提供处理器数据总线和外围数据库之间的接口的外围总线桥，并且包括微控制器内部的多个特殊功能寄存器组块，每个寄存器组块具有相应的输出; 以及寄存器块解码器电路，用于解码中断以提供用于激活所述多个寄存器组块之一的选择输出。

公开(公告)号：US07305543B2

公开(公告)日：2007-12-04

申请号：US10566514

申请日：2004-07-27

申请人： Gregory Goodhue ,  Ata Khan ,  Zhimin Ding

发明人： Gregory Goodhue ,  Ata Khan ,  Zhimin Ding

IPC分类号： G06F9/00

CPC分类号： G06F9/321 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3016 ,  G06F9/35

摘要： All pointer-based accesses require first that the value contained in a pointer register to be read and then that value be used as an address to the appropriate region in random access memory (RAM). As implemented today, this requires two memory read access cycles, each of which takes at least one clock cycle and therefore this implementation does not allow single cycle operation. In accordance with an embodiment of the invention, when an access is performed to pointer memory to read the contents of a pointer, it is the shadow memory that is actually read and that returns the pointer value. Since the shadow memory is made up of pointer registers, a read access involves multiplexing out of appropriate data for the pointer address from these pointer registers to form a target pointer address. This target pointer address is then used as an address to access RAM without the overhead of a clock, since the register access is purely combinatorial and does not require clock-phase related timing as does access to the RAM.

摘要翻译： 所有基于指针的访问首先需要读取指针寄存器中包含的值，然后将该值用作随机存取存储器（RAM）中适当区域的地址。 如今所实现的，这需要两个存储器读取访问周期，每个存储器访问周期至少需要一个时钟周期，因此该实现不允许单周期操作。 根据本发明的实施例，当对指针存储器执行访问以读取指针的内容时，实际上是读取并且返回指针值的影子存储器。 由于阴影存储器由指针寄存器组成，所以读取访问涉及将来自这些指针寄存器的指针地址的适当数据进行复用以形成目标指针地址。 然后，该目标指针地址用作访问RAM的地址，而不需要时钟的开销，因为寄存器访问是纯组合的，并且不需要与访问RAM相关的时钟相关定时。

公开(公告)号：US06658553B1

公开(公告)日：2003-12-02

申请号：US09548987

申请日：2000-04-14

申请人： Zhimin Ding ,  Gregory K. Goodhue ,  Ata R. Khan

发明人： Zhimin Ding ,  Gregory K. Goodhue ,  Ata R. Khan

IPC分类号： G06F1200

CPC分类号： G06F9/30043 ,  G06F9/342 ,  G06F12/0623

摘要： A processing system supports memory access based on distinct memory space access instructions as well as universal access instructions that are independent of memory space partitions. Conventional memory-space dependent instructions, such as MOV, MOVX, and MOVC, provide an optimized addressing scheme, and an extended memory-space independent instruction EMOV provides an optimized code efficiency, processing speed, and ease of code generation. A mapping between the discrete memory space partitions and a “universal” memory space allocation is provided. The processing hardware interprets the universal address to determine the corresponding memory space, and provides the access to an address within that memory space.

摘要翻译： 处理系统支持基于不同存储器空间访问指令的存储器访问以及独立于存储器空间分区的通用访问指令。 传统的与存储器空间相关的指令，例如MOV，MOVX和MOVC，提供了优化的寻址方案，扩展的存储空间独立指令EMOV提供了优化的代码效率，处理速度和代码生成的便利性。 提供了离散存储器空间分区与“通用”存储器空间分配之间的映射。 处理硬件解释通用地址以确定相应的存储器空间，并提供对该存储器空间内的地址的访问。

公开(公告)号：US20060206691A1

公开(公告)日：2006-09-14

申请号：US10566514

申请日：2004-07-27

申请人： Gregory Goodhue ,  Ata Khan ,  Zhimin Ding

发明人： Gregory Goodhue ,  Ata Khan ,  Zhimin Ding

IPC分类号： G06F9/40

CPC分类号： G06F9/321 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3016 ,  G06F9/35

摘要： All Pointer-based accesses require first that the value contained in a pointer register (200a, 200b, 200c, 200d) to be read and then that value be used as an address to the appropriate region in random access memory (RAM) (104). As implemented today, this requires two memory read access cycles, each of which takes at least one clock cycle and therefore this implementation does not allow single cycle operation. In accordance with an embodiment of the invention, when an access is performed to pointer memory (103a, 103b, 103c, 103d) to read the contents of a pointer, it is the shadow memory that is actually read and that returns the pointer value. Since the shadow memory is made up of pointer registers (200a, 200b, 200c, 200d), a read access involves mutliplexing out of appropriate data for the pointer address from these pointer registers (200a, 200b, 200c, 200d) to form a target pointer address. This target pointer address is then used as an address to access RAM (104) without the overhead of a clock, since the register access is purely combinatorial and does not require clock-phase related timing as does access to the RAM (104).

摘要翻译： 所有基于指针的访问首先需要读取指针寄存器（200a，200b，200c，200d）中包含的值，然后将该值用作随机存取存储器（RAM）中适当区域的地址 （104）。 如今所实现的，这需要两个存储器读取访问周期，每个存储器访问周期至少需要一个时钟周期，因此该实现不允许单周期操作。 根据本发明的实施例，当对指针存储器（103a，103b，103c，103d）执行访问以读取指针的内容时，实际上是读取的影子存储器，并且返回 指针值。 由于阴影存储器由指针寄存器（200a，200b，200c，200d）组成，所以读取访问涉及从这些指针寄存器（200a，200b，200c）中针对指针地址的适当数据进行多路复用 ，200 d）以形成目标指针地址。 然后，该目标指针地址用作访问RAM（104）的地址，而不需要时钟的开销，因为寄存器访问是纯组合的，并且不需要与访问RAM（104）一样的时钟相位相关定时。

公开(公告)号：US20060206646A1

公开(公告)日：2006-09-14

申请号：US10566515

申请日：2004-07-29

申请人： Pankaj Shrivastava ,  Gregory Goodhue ,  Ata Khan ,  Zhimin Ding ,  Craig Mackenna

发明人： Pankaj Shrivastava ,  Gregory Goodhue ,  Ata Khan ,  Zhimin Ding ,  Craig Mackenna

IPC分类号： G06F13/24 ,  G06F13/36

CPC分类号： G06F9/4812 ,  G06F9/462 ,  G06F13/26 ,  Y02D10/14 ,  Y02D10/24

摘要： Typically, for processing systems it must be guaranteed that all interrupted program stream parameters are restored before the execution of the first program stream resumes. If during this transfer an interrupt occurs, then all data may not be stored or restored. If the error free storage of the program register contents and other critical first program stream data does not occur, the processor (180) has no way of knowing whether the first program stream data restored to the registers has become corrupt or not. Thus, a novel register architecture (120, 121, 122, 123, 124, 125) is provided that facilitate processing of interrupting program streams without storing and restoring interrupted program stream critical data.

摘要翻译： 通常，对于处理系统，必须保证在第一个程序流的执行恢复之前所有中断的程序流参数都被恢复。 如果在此传输期间发生中断，则所有数据可能不被存储或恢复。 如果不发生程序寄存器内容和其他关键的第一程序流数据的无错误存储，则处理器（180）无法知道还原到寄存器的第一程序流数据是否已经被破坏。 因此，提供了一种新颖的寄存器架构（120,121,122,123,124,125），其便于中断程序流的处理，而不存储和恢复中断的程序流关键数据。

公开(公告)号：US06526463B1

公开(公告)日：2003-02-25

申请号：US09548988

申请日：2000-04-14

申请人： Zhimin Ding ,  Gregory K. Goodhue ,  Ata R. Khan

发明人： Zhimin Ding ,  Gregory K. Goodhue ,  Ata R. Khan

IPC分类号： G06F942

CPC分类号： G06F9/342 ,  G06F9/30043 ,  G06F9/30163 ,  G06F9/30189 ,  G06F9/4486 ,  G06F9/4812

摘要： A processing system with extended addressing capabilities includes a control bit that controls the number of address bytes that are stored onto a program stack. If the control bit is set to a first state, the address is pushed onto the program stack in the same manner as that used for shorter-address legacy devices. If the control bit is set to a second state, the address is pushed onto the program stack using the number of bytes required to contain a longer extended address. This same control bit controls the number of bytes that are popped off the stack upon return from an interrupt subroutine. The state of the control bit is controlled by one or more program instructions, thereby allowing it to assume each state dynamically. This dynamic control of the number of bytes pushed and popped to and from the stack allows for an optimization of stack utilization, and thereby further compatibility with legacy devices and applications.

摘要翻译： 具有扩展寻址能力的处理系统包括控制位，该控制位控制存储在程序堆栈上的地址字节数。 如果控制位设置为第一状态，则以与用于较短地址的传统设备相同的方式将地址推送到程序堆栈。 如果控制位设置为第二个状态，则使用包含较长扩展地址所需的字节数将该地址推送到程序堆栈。 相同的控制位控制从中断子程序返回时从堆栈弹出的字节数。 控制位的状态由一个或多个程序指令控制，从而允许其动态地呈现每个状态。 对堆栈和从堆栈进行弹出的字节数的这种动态控制允许优化堆栈利用率，从而进一步与传统设备和应用程序的兼容性。

公开(公告)号：US09988668B2

公开(公告)日：2018-06-05

申请号：US14128486

申请日：2012-06-25

申请人： Zhimin Ding ,  Fang Wu ,  Li Liu

发明人： Zhimin Ding ,  Fang Wu ,  Li Liu

IPC分类号： C12M1/34 ,  C12Q1/68 ,  B01L7/00

CPC分类号： C12Q1/6806 ,  B01L7/52 ,  B01L2200/028 ,  B01L2200/147 ,  B01L2200/148 ,  B01L2200/16 ,  B01L2300/043 ,  B01L2300/0654 ,  B01L2300/1822 ,  B01L2300/1827

摘要： Described herein is a chip-based apparatus for amplifying nucleic acids, a cartridge housing the apparatus, and methods of using the apparatus for amplification of nucleic acids. More specifically, this invention provides integrated semiconductor chip, manufactured with standard semiconductor manufacturing process, with on-chip circuitry to perform thermal management and optical sensing necessary for amplification of nucleic acids. The apparatus and methods embodied in this invention makes it possible to build a disease diagnosis and prognosis tool that is easy to use, portable and disposable.