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    Spoon-feed initialization in a multiprocessor system
    4.
    发明授权
    Spoon-feed initialization in a multiprocessor system 失效
    多处理器系统中的Spoon-feed初始化

    公开(公告)号：US5682528A

    公开(公告)日：1997-10-28

    申请号：US578889

    申请日：1995-12-22

    申请人： William E. Baker ,  David P. Sonnier ,  Daniel L. Fowler ,  Frank A. Williams

    发明人： William E. Baker ,  David P. Sonnier ,  Daniel L. Fowler ,  Frank A. Williams

    IPC分类号： G06F9/445 ,  G06F9/00

    CPC分类号： G06F15/177 ,  G06F9/4405

    摘要： The present invention provides a mechanism for initial execution of software code by a processor in a multiprocessor system. In the preferred embodiment, the multiprocessor system has registers implemented at a reset vector location in a processor. The registers are first loaded with a sequence of software code, and then a first instruction loop is implemented with that software code. The processor is then released from a reset state, and the first instruction loop is executed. This first instruction loop is capable of being executed for an indefinite length of time, and it can execute software instructions on a periodic basis. The first instruction loop is then modified into a second instruction loop. The first and second instruction loops have at least one different instruction. The processor within the system of multiple processors is thus initialized.

    摘要翻译： 本发明提供了一种用于在多处理器系统中由处理器初始执行软件代码的机制。 在优选实施例中，多处理器系统具有在处理器中的复位向量位置处实现的寄存器。 寄存器首先加载一系列软件代码，然后使用该软件代码实现第一个指令循环。 然后处理器从复位状态释放，并且执行第一指令循环。 该第一指令循环能够执行不确定的时间长度，并且可以周期性地执行软件指令。 然后将第一个指令循环修改为第二个指令循环。 第一和第二指令循环至少有一个不同的指令。 因此，在多个处理器的系统内的处理器被初始化。

    Routing arbitration for shared resources
    6.
    发明授权
    Routing arbitration for shared resources 失效
    共享资源路由仲裁

    公开(公告)号：US5710549A

    公开(公告)日：1998-01-20

    申请号：US483663

    申请日：1995-06-07

    申请人： Robert W. Horst ,  William J. Watson ,  David P. Sonnier

    发明人： Robert W. Horst ,  William J. Watson ,  David P. Sonnier

    IPC分类号： G06F7/507 ,  G06F7/508 ,  G06F11/18 ,  G06F13/14 ,  G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  H04L12/56 ,  H04Q1/18

    CPC分类号： H04L45/00 ,  G06F13/14 ,  G06F13/4022

    摘要： A data communicating device, having a number of inputs whereat data is received for communication from one of a number of outputs of the device, includes apparatus for providing two levels of arbitration to select one of the inputs for data communication to an output. The first (lower) level of arbitration bases selection upon a round-robin order; the second (higher) arbitration level selects inputs based upon an indication from an input of an undue wait for access to the output over a period of time. Each input is provided a modulo-N counter, and a digital counter. Each time an input contends for access to an output and loses to selection by the output to another input, the modulo-N counter is incremented by an assigned value for that input. When N is exceed without access, the digital counter is incremented. The content of the counter operates to force the high-level arbitration.

    摘要翻译： 一种数据通信设备，具有从设备的多个输出端之一接收用于通信的数据的多个输入的数据通信设备，包括用于提供两个级别的仲裁以选择输入之一进行数据通信的设备。 第一（较低）的仲裁程序依循循环次序进行选择; 第二（较高）仲裁级别基于来自输入的指示在一段时间内选择输入，该输入不正确等待访问输出。 每个输入都提供一个模N计数器和一个数字计数器。 每当输入争用访问输出并输入到另一个输入的选择时，模N计数器将增加该输入的分配值。 当N超过无接入时，数字计数器递增。 柜台的内容是迫使高层仲裁。

    Latency reduction and routing arbitration for network message routers
    7.
    发明授权
    Latency reduction and routing arbitration for network message routers 失效
    网络消息路由器的延迟减少和路由仲裁

    公开(公告)号：US5694121A

    公开(公告)日：1997-12-02

    申请号：US469756

    申请日：1995-06-06

    申请人： John C. Krause ,  William J. Watson ,  David P. Sonnier ,  Robert W. Horst

    发明人： John C. Krause ,  William J. Watson ,  David P. Sonnier ,  Robert W. Horst

    IPC分类号： G06F13/14 ,  G06F13/40 ,  H04L12/56 ,  H04Q9/00

    CPC分类号： H04L45/00 ,  G06F13/14 ,  G06F13/4022

    摘要： A data communicating device, having a number of inputs whereat data is received for communication from one of a number of outputs of the device, includes apparatus for selecting one of the inputs based upon a comparison of accumulated bias values that can change over time when an input is kept waiting. Each input is provided an assigned bias value from which is developed the accumulated bias value that is compared with that of other inputs arbitrating for access to an output. The output selects one of the inputs, based upon the comparison, and the accumulated bias value of the selected input is diminished by the sum of the assigned bias values of the inputs participating in the arbitration, but not selected, while the accumulated bias values of the other participants are each increased by their corresponding assigned bias values. Thereby, numbers of inputs having data destined for the same output will have their chance of gaining access to the output increased the longer they wait; conversely, inputs which do gain access have their chances for immediate subsequent access decreased in favor of allowing other inputs access.

    摘要翻译： 一种数据通信设备，具有从该设备的多个输出中的一个接收用于通信的数据的多个输入的数据通信设备，包括：用于基于当随时间变化的累积偏差值的比较来选择输入中的一个的设备 输入一直在等待。 为每个输入提供一个分配的偏置值，从中产生与累加偏差值相比较的累加偏差值，该值与仲裁用于访问输出的其他输入进行比较。 输出根据比较来选择一个输入，并且所选择的输入的累积偏差值减去参与仲裁但不被选择的输入的所分配的偏置值的总和，而积分的偏差值 其他参与者各自增加其相应的分配偏差值。 因此，具有输出到相同输出的数据的输入的数量将有机会获得对输出的访问增加等待的时间越长; 相反，获得访问权的输入端有可能立即进行访问，有利于允许其他输入访问。

    Transpose table biased arbitration scheme
    8.
    发明授权
    Transpose table biased arbitration scheme 失效
    转置表偏向仲裁方案

    公开(公告)号：US06631131B1

    公开(公告)日：2003-10-07

    申请号：US09312923

    申请日：1999-05-17

    申请人： David P. Sonnier ,  William J. Watson ,  Robert B. Mizell ,  Robert W. Horst

    发明人： David P. Sonnier ,  William J. Watson ,  Robert B. Mizell ,  Robert W. Horst

    IPC分类号： H04L1256

    CPC分类号： H04L49/90

    摘要： A biased arbitration technique utilizes a transpose table to arbitrate access to a shared resource. Each column of transpose table is a binary bias vector encoding a bias value assigned to one of the requestors. The rows of the table are fetched to assure that requestors having high bias values are granted more frequent access to the shared resource. A look-ahead feature skips rows having all zeros and an unbiased cycle that assures all requesting ports are serviced regardless of their bias values.

    摘要翻译： 偏向仲裁技术利用转置表仲裁对共享资源的访问。 转置表的每一列是编码分配给其中一个请求者的偏移值的二进制偏差向量。 提取表的行以确保具有高偏差值的请求者被更频繁地访问共享资源。 先行功能跳过具有全零和不偏倚周期的行，确保所有请求端口都被服务，而不管其偏差值如何。

    Method and apparatus for configuring routing paths of a network communicatively interconnecting a number of processing elements
    9.
    发明授权
    Method and apparatus for configuring routing paths of a network communicatively interconnecting a number of processing elements 失效
    用于配置通信地互连多个处理元件的网络的路由路径的方法和装置

    公开(公告)号：US5983269A

    公开(公告)日：1999-11-09

    申请号：US764115

    申请日：1996-12-09

    申请人： H. David Mattson ,  William J. Watson ,  David J. Garcia ,  David P. Sonnier

    发明人： H. David Mattson ,  William J. Watson ,  David J. Garcia ,  David P. Sonnier

    IPC分类号： H04L12/56 ,  H04L29/12 ,  G06F11/00

    CPC分类号： H04L45/02 ,  H04L29/12009 ,  H04L61/00

    摘要： A multiple processing system, comprises at least a pair of processor units communicatively connected to a number of peripheral devices through a network that includes routing devices interconnected to route information in the form of message packets sent between the processor units and peripheral devices. Data describing the topographical interconnections of the system elements is maintained with the system. A service processor accesses the data, determines therefrom the topographical interconnections forming the network, assigns addresses/identifications to the system elements, and configures the router devices to establish the most direct routes between system elements for message packets sent on the network.

    摘要翻译： 多处理系统包括至少一对通过网络通信地连接到多个外围设备的处理器单元，所述网络包括以处理器单元和外围设备之间发送的消息分组形式的路由信息​​互连的路由设备。 使用系统维护描述系统元件的地形互连的数据。 服务处理器访问数据，从而确定构成网络的地形互连，为系统元件分配地址/标识，并配置路由器设备，以在网络上发送的消息分组之间建立最直接的路由。

    Method of management of a circular queue for asynchronous access
    10.
    发明授权
    Method of management of a circular queue for asynchronous access 失效
    用于异步访问的循环队列的管理方法

    公开(公告)号：US6145061A

    公开(公告)日：2000-11-07

    申请号：US3201

    申请日：1998-01-07

    申请人： David J. Garcia ,  David P. Sonnier

    发明人： David J. Garcia ,  David P. Sonnier

    IPC分类号： G06F5/06 ,  G06F13/00

    CPC分类号： G06F5/06

    摘要： A circular queue is asynchronously accessed and managed by two separate processing elements. Each data element is added to the queue together with a zero data element that both marks the tail of the queue and signifies that the queue is empty. Data elements are removed from the queue in the order in which they were stored (first-in-first-out) and a manner that allows multiple, concurrent access to the queue. When the queue is accessed to remove a data element the element is first tested. If it is non-zero, the removal process continues; if zero, the queue is considered empty. The management of the queue permits dynamic re-sizing (i.e., making the queue larger or smaller) while data elements are being added and/or removed.

    摘要翻译： 循环队列由两个单独的处理元素异步访问和管理。 每个数据元素与零数据元素一起添加到队列中，这两个元素都标记队列的尾部，并表示队列为空。 数据元素按照存储顺序（先进先出）从队列中删除，并允许多个并发访问队列。 当访问队列以删除数据元素时，首先测试该元素。 如果不为零，则删除过程将继续; 如果为零，则队列被认为是空的。 在添加和/或移除数据元素的同时，队列的管理允许动态重新调整大小（即使队列更大或更小）。