公开(公告)号：US06879486B1

公开(公告)日：2005-04-12

申请号：US10076226

申请日：2002-02-14

申请人： Randall G. Banton ,  Don W. Blanchet ,  John R. Freeburn, Jr. ,  Jason E. Bardo ,  Mike W. Gust ,  Paul N. Zuidema

发明人： Randall G. Banton ,  Don W. Blanchet ,  John R. Freeburn, Jr. ,  Jason E. Bardo ,  Mike W. Gust ,  Paul N. Zuidema

IPC分类号： H05K7/20

CPC分类号： H05K7/20563

摘要： An improved circuit board assembly includes a cover or other member disposed adjacent to the substrate and, for example, spaced therefrom so as to define a plenum. Self-aligning heat sinks (or other heat dissipative elements) are spring-mounted (or otherwise resiliently mounted) to the cover and, thereby, placed in thermal contact with one or more of the circuit components. Flow-diverting elements are provided, e.g., so that the overall impedance of the board substantially matches that of one or more of the other circuit boards in a common chassis. The circuit board cover can be adapted to provide thermal and/or electromagnetic emission control, as well as shock and vibration. A connector arrangement provides electrical, mechanical and/or other operational coupling between the circuit board and a chassis regardless of whether the board is disposed in a slot on a first (e.g., upper) side of a source of cooling air for the chassis or on a second (e.g, lower) opposite side of that source. A circuit board can have one or two portions, each with an air flow inlet edge through which cooling air flow is received and an air flow outlet edge through which the air flow exists. An improved chassis for mounting of such circuit boards can have a center air inlet. It can also have a circuit-board insertion slot with a first air flow aperture disposed adjacent to a first edge of an inserted circuit board and a second apertures disposed adjacent to a second edge of the board. These apertures can be sized so that the impedance to air flow to a circuit board inserted in the slot substantially matches that to one or more other boards in the chassis. Such slots can form part of a card cage that is vacuum or dip brazed, or manufactured by an alternate process yielding a cage of desired structural stiffness and air-flow/interference sealing. The circuit boards and chassis can include an air and/or electromagnetic interference (EMI) seal which forms as the circuit board is inserted into the chassis slot.

公开(公告)号：US06759588B1

公开(公告)日：2004-07-06

申请号：US10076124

申请日：2002-02-14

申请人： Randall G. Banton ,  Don W. Blanchet ,  John R. Freeburn, Jr. ,  Jason E. Bardo ,  A. Gregory Rocco, Jr. ,  Mike W. Gust ,  Paul N. Zuidema

发明人： Randall G. Banton ,  Don W. Blanchet ,  John R. Freeburn, Jr. ,  Jason E. Bardo ,  A. Gregory Rocco, Jr. ,  Mike W. Gust ,  Paul N. Zuidema

IPC分类号： H05K900

CPC分类号： H05K7/20727

摘要： An improved circuit board assembly includes a cover or other member disposed adjacent to the substrate and, for example, spaced therefrom so as to define a plenum. Self-aligning heat sinks (or other heat dissipative elements) are spring-mounted (or otherwise resiliently mounted) to the cover and, thereby, placed in thermal contact with one or more of the circuit components. Flow-diverting elements are provided, e.g., so that the overall impedance of the board substantially matches that of one or more of the other circuit boards in a common chassis. The circuit board cover can be adapted to provide thermal and/or electromagnetic emission control, as well as shock and vibration. A connector arrangement provides electrical, mechanical and/or other operational coupling between the circuit board and a chassis regardless of whether the board is disposed in a slot on a first (e.g., upper) side of a source of cooling air for the chassis or on a second (e.g., lower) opposite side of that source. A circuit board can have one or two portions, each with an air flow inlet edge through which cooling air flow is received and an air flow outlet edge through which the air flow exits. An improved chassis for mounting of such circuit boards can have a center air inlet. It can also have a circuit-board insertion slot with a first air flow aperture disposed adjacent to a first edge of an inserted circuit board and a second apertures disposed adjacent to a second edge of the board. These apertures can be sized so that the impedance to air flow to a circuit board inserted in the slot substantially matches that to one or more other boards in the chassis. Such slots can form part of a card cage that is vacuum or dip brazed, or manufactured by an alternate process welding a cage of desired structural stiffness and air-flow/interference sealing. The circuit boards and chassis can include an air and/or electromagnetic interference (EMI) seal which forms as the circuit board is inserted into the chassis slot.

公开(公告)号：US6073251A

公开(公告)日：2000-06-06

申请号：US871077

申请日：1997-06-09

申请人： Douglas E. Jewett ,  Tom Bereiter ,  Bryan Vetter ,  Randall G. Banton ,  Richard W. Cutts, Jr. ,  Donald C. Westbrook, deceased ,  Krayn W. Fey, Jr. ,  John Posdro ,  Kenneth C. DeBacker ,  Nikhil A. Mehta

发明人： Douglas E. Jewett ,  Tom Bereiter ,  Bryan Vetter ,  Randall G. Banton ,  Richard W. Cutts, Jr. ,  Donald C. Westbrook, deceased ,  Krayn W. Fey, Jr. ,  John Posdro ,  Kenneth C. DeBacker ,  Nikhil A. Mehta

IPC分类号： G06F1/12 ,  G06F1/30 ,  G06F11/07 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F11/22 ,  G06F11/273

CPC分类号： G06F1/12 ,  G06F1/30 ,  G06F11/0709 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/1441 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/181 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2007 ,  G06F11/2015 ,  G06F11/2005 ,  G06F11/22 ,  G06F11/2736

摘要： A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of identical (redundant) processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown.

摘要翻译： 容错配置的计算机系统使用执行相同指令流的多个相同的CPU，在存储相同数据的副本的CPU的地址空间中具有多个相同的存储器模块。 系统检测CPU和内存模块中的故障，并使故障单元脱机，并继续使用良好的单元进行操作。 故障单元可以更换并重新集成到系统中，无需关闭。 多个CPU松动地同步，如通过检测诸如内存引用的事件，并阻止其他任何CPU之前的事件，直到所有同时执行该功能; 可以通过确保所有CPU在其指令流中的相同点实现中断来实现中断。 通过单独的CPU到内存总线的内存引用在每个内存模块的三个独立端口上进行投票。 使用两个相同的I / O总线实现I / O功能，每个总线单独耦合到只有一个存储器模块。 许多I / O处理器耦合到两个I / O总线。 I / O设备通过一对相同（冗余）处理器访问，但只有一个被指定为主动控制给定的设备; 然而，在一个I / O处理器发生故障的情况下，I / O设备可以被另一个I / O设备访问，而不需要系统关闭。

公开(公告)号：US5588111A

公开(公告)日：1996-12-24

申请号：US381467

申请日：1995-01-31

申请人： Richard W. Cutts, Jr. ,  Randall G. Banton ,  Douglas E. Jewett

发明人： Richard W. Cutts, Jr. ,  Randall G. Banton ,  Douglas E. Jewett

IPC分类号： G06F11/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00

CPC分类号： G06F9/3863 ,  G06F11/0724 ,  G06F11/1641 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/18 ,  G06F11/184 ,  G06F11/185 ,  G06F11/2017 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3885 ,  G06F11/0757 ,  G06F11/1008 ,  G06F11/1405 ,  G06F11/1415 ,  G06F11/1679 ,  G06F11/181 ,  G06F11/182 ,  G06F11/20 ,  G06F11/2015 ,  G06F2201/85 ,  G11C29/74

摘要： A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

摘要翻译： 容错配置的计算机系统使用执行相同指令流的多个相同的CPU，在存储相同数据的副本的CPU的地址空间中具有多个相同的存储器模块。 多个CPU松动地同步，如通过检测诸如内存引用的事件，并阻止其他任何CPU之前的事件，直到所有同时执行该功能; 可以通过确保所有CPU在其指令流中的相同点实现中断来实现中断。 I / O设备通过一对相同（冗余）I / O处理器访问，但只有一个被指定为主动控制给定的设备; 然而，在一个I / O处理器发生故障的情况下，I / O设备可以被另一个I / O设备访问，而不需要系统关闭，即仅在指令控制下重新指定I / O设备的寄存器的地址。

公开(公告)号：US5276823A

公开(公告)日：1994-01-04

申请号：US664495

申请日：1991-03-05

申请人： Richard W. Cutts, Jr. ,  Randall G. Banton ,  Douglas E. Jewett

发明人： Richard W. Cutts, Jr. ,  Randall G. Banton ,  Douglas E. Jewett

IPC分类号： G06F11/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00

CPC分类号： G06F9/3863 ,  G06F11/0724 ,  G06F11/1641 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/18 ,  G06F11/184 ,  G06F11/185 ,  G06F11/2017 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3885 ,  G06F11/0757 ,  G06F11/1008 ,  G06F11/1405 ,  G06F11/1415 ,  G06F11/1679 ,  G06F11/181 ,  G06F11/182 ,  G06F11/20 ,  G06F11/2015 ,  G06F2201/85 ,  G11C29/74

摘要： A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

摘要翻译： 容错配置的计算机系统使用执行相同指令流的多个相同的CPU，在存储相同数据的副本的CPU的地址空间中具有多个相同的存储器模块。 多个CPU松动地同步，如通过检测诸如内存引用的事件，并阻止其他任何CPU之前的事件，直到所有同时执行该功能; 可以通过确保所有CPU在其指令流中的相同点实现中断来实现中断。 I / O设备通过一对相同（冗余）I / O处理器访问，但只有一个被指定为主动控制给定的设备; 然而，在一个I / O处理器发生故障的情况下，I / O设备可以被另一个I / O设备访问，而不需要系统关闭，即仅在指令控制下重新指定I / O设备的寄存器的地址。

公开(公告)号：US06661657B1

公开(公告)日：2003-12-09

申请号：US10076133

申请日：2002-02-14

申请人： Randall G. Banton ,  Don W. Blanchet ,  John R. Freeburn, Jr. ,  Jason E. Bardo ,  Mike W. Gust ,  Paul N. Zuidema

发明人： Randall G. Banton ,  Don W. Blanchet ,  John R. Freeburn, Jr. ,  Jason E. Bardo ,  Mike W. Gust ,  Paul N. Zuidema

IPC分类号： H05K720

CPC分类号： H05K7/20563 ,  G06F1/181 ,  G06F1/183 ,  G06F1/20

摘要： An improved circuit board assembly includes a cover or other member disposed adjacent to the substrate and, for example, spaced therefrom so as to define a plenum. Self-aligning heat sinks (or other heat dissipative elements) are spring-mounted (or otherwise resiliently mounted) to the cover and, thereby, placed in thermal contact with one or more of the circuit components. Flow-diverting elements are provided, e.g., so that the overall impedance of the board substantially matches that of one or more of the other circuit boards in a common chassis. The circuit board cover can be adapted to provide thermal and/or electromagnetic emission control, as well as shock and vibration. A connector arrangement provides electrical, mechanical and/or other operational coupling between the circuit board and a chassis regardless of whether the board is disposed in a slot on a first (e.g., upper) side of a source of cooling air for the chassis or on a second (e.g., lower) opposite side of that source. A circuit board can have one or two portions, each with an air flow inlet edge through which cooling air flow is received and an air flow outlet edge through which the air flow exits. An improved chassis for mounting of such circuit boards can have a center air inlet. It can also have a circuit-board insertion slot with a first air flow aperture disposed adjacent to a first edge of an inserted circuit board and a second apertures disposed adjacent to a second edge of the board. These apertures can be sized so that the impedance to air flow to a circuit board inserted in the slot substantially matches that to one or more other boards in the chassis. Such slots can form part of a card cage that is vacuum or dip brazed, or manufactured by an alternate process yielding a cage of desired structural stiffness and air-flow/interference sealing. The circuit boards and chassis can include an air and/or electromagnetic interference (EMI) seal which forms as the circuit board is inserted into the chassis slot.

公开(公告)号：US06263452B1

公开(公告)日：2001-07-17

申请号：US09226960

申请日：1999-01-08

申请人： Douglas E. Jewett ,  Tom Bereiter ,  Bryan Vetter ,  Randall G. Banton ,  Richard W. Cutts, Jr. ,  Donald C. Westbrook ,  Krayn W. Fey, Jr. ,  John Posdro ,  Kenneth C. Debacker ,  Nikhil A. Mehta

发明人： Douglas E. Jewett ,  Tom Bereiter ,  Bryan Vetter ,  Randall G. Banton ,  Richard W. Cutts, Jr. ,  Donald C. Westbrook ,  Krayn W. Fey, Jr. ,  John Posdro ,  Kenneth C. Debacker ,  Nikhil A. Mehta

IPC分类号： G06F1118

CPC分类号： G06F1/12 ,  G06F1/30 ,  G06F11/0709 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/1441 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/181 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2005 ,  G06F11/2007 ,  G06F11/2015 ,  G06F11/22 ,  G06F11/2736

摘要： A computer system in a fault-tolerant configuration employees multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown.

摘要翻译： 在容错配置中的计算机系统雇用执行相同指令流的多个相同的CPU，在存储相同数据的副本的CPU的地址空间中具有多个相同的存储器模块。 系统检测CPU和内存模块中的故障，并使故障单元脱机，并继续使用良好的单元进行操作。 故障单元可以更换并重新集成到系统中，无需关闭。 多个CPU松动地同步，如通过检测诸如内存引用的事件，并阻止其他任何CPU之前的事件，直到所有同时执行该功能; 可以通过确保所有CPU在其指令流中的相同点实现中断来实现中断。 通过单独的CPU到内存总线的内存引用在每个内存模块的三个独立端口上进行投票。 使用两个相同的I / O总线实现I / O功能，每个总线单独耦合到只有一个存储器模块。 许多I / O处理器耦合到两个I / O总线。 I / O设备通过一对相同（冗余）I / O处理器访问，但只有一个被指定为主动控制给定的设备; 然而，在一个I / O处理器发生故障的情况下，I / O设备可以被另一个I / O设备访问，而不需要系统关闭。

公开(公告)号：US5751932A

公开(公告)日：1998-05-12

申请号：US485217

申请日：1995-06-07

申请人： Robert W. Horst ,  William Edward Baker ,  Randall G. Banton ,  John Michael Brown ,  William F. Bruckert ,  William Patterson Bunton ,  Gary F. Campbell ,  John Deane Coddington ,  Richard W. Cutts, Jr. ,  Barry Lee Drexler ,  Harry Frank Elrod ,  Daniel L. Fowler ,  David J. Garcia ,  Paul N. Hintikka ,  Geoffrey I. Iswandhi ,  Douglas Eugene Jewett ,  Curtis Willard Jones, Jr. ,  James Stevens Klecka ,  John C. Krause ,  Stephen G. Low ,  Susan Stone Meredith ,  Steven C. Meyers ,  David P. Sonnier ,  William Joel Watson ,  Patricia L. Whiteside ,  Frank A. Williams ,  Linda Ellen Zalzala

发明人： Robert W. Horst ,  William Edward Baker ,  Randall G. Banton ,  John Michael Brown ,  William F. Bruckert ,  William Patterson Bunton ,  Gary F. Campbell ,  John Deane Coddington ,  Richard W. Cutts, Jr. ,  Barry Lee Drexler ,  Harry Frank Elrod ,  Daniel L. Fowler ,  David J. Garcia ,  Paul N. Hintikka ,  Geoffrey I. Iswandhi ,  Douglas Eugene Jewett ,  Curtis Willard Jones, Jr. ,  James Stevens Klecka ,  John C. Krause ,  Stephen G. Low ,  Susan Stone Meredith ,  Steven C. Meyers ,  David P. Sonnier ,  William Joel Watson ,  Patricia L. Whiteside ,  Frank A. Williams ,  Linda Ellen Zalzala

IPC分类号： G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14

CPC分类号： G01R31/31727 ,  G06F1/12 ,  G06F11/10 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1679 ,  G06F11/1687 ,  G06F12/0815 ,  G06F12/1483 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40 ,  G01R31/318533 ,  G06F11/004 ,  G06F11/1044 ,  G06F11/167 ,  G06F11/1683 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F2201/845 ,  H04L12/56

摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

摘要翻译： 多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过也互连子处理器系统的路由设备互连。 任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信。 CPU被构造为以两种模式之一操作：两个CPU彼此独立地操作的单工模式，以及CPU以锁步同步操作的双工模式，以基本上执行相同指令流的每条指令 同一时间。 I / O设备和CPU之间的通信是分组消息。 来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息数据包。 CPU和I / O设备可以写入或读取系统的CPU的存储器。 存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个内存访问被拒绝。

公开(公告)号：US4633461A

公开(公告)日：1986-12-30

申请号：US752672

申请日：1985-07-08

申请人： Randall G. Banton ,  Rajiv Bhatia ,  Donald B. Grust ,  David R. Johnson ,  Joseph G. Kneuer ,  Kuang-Shin Lin ,  Henry S. McDonald ,  David A. Poppe ,  Jeffrey W. Reedy ,  Richard T. Wurth

发明人： Randall G. Banton ,  Rajiv Bhatia ,  Donald B. Grust ,  David R. Johnson ,  Joseph G. Kneuer ,  Kuang-Shin Lin ,  Henry S. McDonald ,  David A. Poppe ,  Jeffrey W. Reedy ,  Richard T. Wurth

IPC分类号： H04Q11/04

CPC分类号： H04Q11/0407

摘要： A multi-stage time division switch interconnects processors communicating over one or more channels on time division lines. One of the processors is designated as a common processor to provide the switching "mapping" information for the various stages of the switch sending the switching information to the memory and logic of each switched stage over dedicated channels which include channels on the time division line emanating from the common processor and time division channels which pass through several switches until the memory of the applicable switch is accessed.

摘要翻译： 多级时分交换机将处理器通过时分线上的一个或多个信道进行通信。 其中一个处理器被指定为公共处理器，以提供交换各个阶段的切换“映射”信息，该切换信号通过专用信道将切换信息发送到存储器和每个切换级的逻辑，这些专用信道包括时分线上发出的信道 来自通过多个交换机的公共处理器和时分信道直到访问适用的交换机的存储器。

公开(公告)号：US06781831B1

公开(公告)日：2004-08-24

申请号：US10076207

申请日：2002-02-14

申请人： Randall G. Banton ,  Don W. Blanchet ,  Jason E. Bardo ,  Mike W. Gust ,  Paul N. Zuidema

发明人： Randall G. Banton ,  Don W. Blanchet ,  Jason E. Bardo ,  Mike W. Gust ,  Paul N. Zuidema

IPC分类号： H05K720

CPC分类号： H05K7/20727 ,  G06F1/183 ,  G06F1/20

摘要： An improved circuit board assembly includes a cover or other member disposed adjacent to the substrate and, for example, spaced therefrom so as to define a plenum. Self-aligning heat sinks (or other heat dissipative elements) are spring-mounted (or otherwise resiliently mounted) to the cover and, thereby, placed in thermal contact with one or more of the circuit components. Flow-diverting elements are provided, e.g., so that the overall impedance of the board substantially matches that of one or more of the other circuit boards in a common chassis. The circuit board cover can be adapted to provide thermal and/or electromagnetic emission control, as well as shock and vibration. A connector arrangement provides electrical, mechanical and/or other operational coupling between the circuit board and a chassis regardless of whether the board is disposed in a slot on a first (e.g., upper) side of a source of cooling air for the chassis or on a second (e.g., lower) opposite side of that source. A circuit board can have one or two portions, each with an air flow inlet edge through which cooling air flow is received and an air flow outlet edge through which the air flow exits. An improved chassis for mounting of such circuit boards can have a center air inlet. It can also have a circuit-board insertion slot with a first air flow aperture disposed adjacent to a first edge of an inserted circuit board and a second apertures disposed adjacent to a second edge of the board. These apertures can be sized so that the impedance to air flow to a circuit board inserted in the slot substantially matches that to one or more other boards in the chassis. Such slots can form part of a card cage that is vacuum or dip brazed, or manufactured by an alternate process yielding a cage of desired structural stiffness and air-flow/interference sealing. The circuit boards and chassis can include an air and/or electromagnetic interference (EMI) seal which forms as the circuit board is inserted into the chassis slot.