公开(公告)号：US06171935B2

公开(公告)日：2001-01-09

申请号：US09317694

申请日：1999-05-24

申请人： Paul Nance ,  Wolfgang Werner

发明人： Paul Nance ,  Wolfgang Werner

IPC分类号： H01L2120

CPC分类号： H01L29/7802 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/30604 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0873 ,  H01L29/1095 ,  H01L29/66712 ,  Y10S438/969

摘要： A process for producing an epitaxial layer with laterally varying doping includes the following steps: (a) applying a patterned insulator layer to a semiconductor body; (b) growing a first epitaxial layer on the semiconductor body and the patterned insulator layer so that monocrystalline regions are formed over the semiconductor body and polycrystalline regions are formed over the patterned insulator layer, the angle of inclination (&agr;) of the interface between the monocrystalline regions and the polycrystalline regions depending on the grain size of the polycrystalline regions; (c) removing the polycrystalline regions and the insulator layer, and (d) growing a second epitaxial layer which, together with the monocrystalline regions of the first epitaxial layer, forms the epitaxial layer.

摘要翻译： 用于制造具有横向变化掺杂的外延层的方法包括以下步骤：（a）将图案化的绝缘体层施加到半导体本体; （b）在半导体主体和图案化的绝缘体层上生长第一外延层，使得在半导体主体上形成单晶区域，并且多晶区域形成在图案化的绝缘体层之上，其中界面的倾斜角（α） 单晶区域和多晶区域取决于多晶区域的晶粒尺寸; （c）去除多晶区域和绝缘体层，以及（d）生长第二外延层，其与第一外延层的单晶区域一起形成外延层。

公开(公告)号：US06734676B2

公开(公告)日：2004-05-11

申请号：US09997984

申请日：2001-11-29

申请人： Ludwig Leipold ,  Paul Nance

发明人： Ludwig Leipold ,  Paul Nance

IPC分类号： F02P1700

CPC分类号： F02P3/045 ,  F02D2041/2017 ,  F02D2041/2031

摘要： A method for generating a control signal after a predeterminable period of time is described. The method includes applying a voltage to an inductor at a beginning of a time measurement; and outputting, via a current threshold value detector, the control signal if a current through the inductor exceeds a predeterminable threshold value. The invention also relates to a timing circuit.

摘要翻译： 描述了在可预定的时间段之后产生控制信号的方法。 该方法包括在时间测量开始时向电感器施加电压; 并且如果通过电感器的电流超过可预定的阈值，则经由电流阈值检测器输出控制信号。 本发明还涉及定时电路。

公开(公告)号：US06310331B1

公开(公告)日：2001-10-30

申请号：US09633708

申请日：2000-08-07

申请人： Paul Nance ,  Peter Sommer ,  Jenoe Tihanyi ,  Ludwig Leipold

发明人： Paul Nance ,  Peter Sommer ,  Jenoe Tihanyi ,  Ludwig Leipold

IPC分类号： H05B102

CPC分类号： F02P3/0421 ,  Y10T307/773

摘要： A circuit configuration for driving an ignition coil includes a first semiconductor switch having a load path connected in series with a primary winding of the ignition coil, and having a control electrode, which is driven in accordance with a first drive signal. The circuit configuration further includes a second semiconductor switch having a load path connected in parallel with the primary winding and having a control electrode, which is driven in accordance with a second drive signal.

摘要翻译： 用于驱动点火线圈的电路结构包括具有与点火线圈的初级绕组串联连接的负载路径的第一半导体开关，并且具有根据第一驱动信号驱动的控制电极。 电路结构还包括第二半导体开关，其具有与初级绕组并联连接的负载路径，并具有根据第二驱动信号驱动的控制电极。

公开(公告)号：US6156621A

公开(公告)日：2000-12-05

申请号：US158252

申请日：1998-09-22

申请人： Paul Nance ,  Ludwig Leipold ,  Wolfgang Werner

发明人： Paul Nance ,  Ludwig Leipold ,  Wolfgang Werner

IPC分类号： H01L21/60 ,  H01L23/14 ,  H01L29/06 ,  H01L21/76

CPC分类号： H01L24/80 ,  H01L23/147 ,  H01L29/0657 ,  H01L2224/83894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/14 ,  Y10S438/977

摘要： A method for fabricating direct wafer bond Si/SiO.sub.2 /Si substrates in which trenches are etched into a rear side of a device wafer. Subsequently, the rear side of the device wafer is ground. The device wafer is then placed by its front side onto the carrier wafer and the wafers are cross-linked to each other. The method has the advantage that a trench depth is no longer defined by an inaccurate etching process but rather by a thinning-back process that can be precisely controlled.

摘要翻译： 用于制造直接晶片接合Si / SiO 2 / Si衬底的方法，其中沟槽被蚀刻到器件晶片的后侧。 随后，将器件晶片的背面研磨。 然后将器件晶片由其前侧放置在载体晶片上，并且晶片彼此交联。 该方法具有以下优点：沟槽深度不再由不准确的蚀刻工艺限定，而是通过能够被精确控制的薄化后处理来限定。