公开(公告)号：US06734676B2

公开(公告)日：2004-05-11

申请号：US09997984

申请日：2001-11-29

申请人： Ludwig Leipold ,  Paul Nance

发明人： Ludwig Leipold ,  Paul Nance

IPC分类号： F02P1700

CPC分类号： F02P3/045 ,  F02D2041/2017 ,  F02D2041/2031

摘要： A method for generating a control signal after a predeterminable period of time is described. The method includes applying a voltage to an inductor at a beginning of a time measurement; and outputting, via a current threshold value detector, the control signal if a current through the inductor exceeds a predeterminable threshold value. The invention also relates to a timing circuit.

摘要翻译： 描述了在可预定的时间段之后产生控制信号的方法。 该方法包括在时间测量开始时向电感器施加电压; 并且如果通过电感器的电流超过可预定的阈值，则经由电流阈值检测器输出控制信号。 本发明还涉及定时电路。

公开(公告)号：US06310331B1

公开(公告)日：2001-10-30

申请号：US09633708

申请日：2000-08-07

申请人： Paul Nance ,  Peter Sommer ,  Jenoe Tihanyi ,  Ludwig Leipold

发明人： Paul Nance ,  Peter Sommer ,  Jenoe Tihanyi ,  Ludwig Leipold

IPC分类号： H05B102

CPC分类号： F02P3/0421 ,  Y10T307/773

摘要： A circuit configuration for driving an ignition coil includes a first semiconductor switch having a load path connected in series with a primary winding of the ignition coil, and having a control electrode, which is driven in accordance with a first drive signal. The circuit configuration further includes a second semiconductor switch having a load path connected in parallel with the primary winding and having a control electrode, which is driven in accordance with a second drive signal.

摘要翻译： 用于驱动点火线圈的电路结构包括具有与点火线圈的初级绕组串联连接的负载路径的第一半导体开关，并且具有根据第一驱动信号驱动的控制电极。 电路结构还包括第二半导体开关，其具有与初级绕组并联连接的负载路径，并具有根据第二驱动信号驱动的控制电极。

公开(公告)号：US6156621A

公开(公告)日：2000-12-05

申请号：US158252

申请日：1998-09-22

申请人： Paul Nance ,  Ludwig Leipold ,  Wolfgang Werner

发明人： Paul Nance ,  Ludwig Leipold ,  Wolfgang Werner

IPC分类号： H01L21/60 ,  H01L23/14 ,  H01L29/06 ,  H01L21/76

CPC分类号： H01L24/80 ,  H01L23/147 ,  H01L29/0657 ,  H01L2224/83894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/14 ,  Y10S438/977

摘要： A method for fabricating direct wafer bond Si/SiO.sub.2 /Si substrates in which trenches are etched into a rear side of a device wafer. Subsequently, the rear side of the device wafer is ground. The device wafer is then placed by its front side onto the carrier wafer and the wafers are cross-linked to each other. The method has the advantage that a trench depth is no longer defined by an inaccurate etching process but rather by a thinning-back process that can be precisely controlled.

摘要翻译： 用于制造直接晶片接合Si / SiO 2 / Si衬底的方法，其中沟槽被蚀刻到器件晶片的后侧。 随后，将器件晶片的背面研磨。 然后将器件晶片由其前侧放置在载体晶片上，并且晶片彼此交联。 该方法具有以下优点：沟槽深度不再由不准确的蚀刻工艺限定，而是通过能够被精确控制的薄化后处理来限定。

公开(公告)号：US06774682B2

公开(公告)日：2004-08-10

申请号：US10026241

申请日：2001-12-21

申请人： Thomas Theobald ,  Ludwig Leipold

发明人： Thomas Theobald ,  Ludwig Leipold

IPC分类号： H03B100

CPC分类号： H03K17/168 ,  H03K17/163

摘要： A circuit configuration for driving a semiconductor switching element includes an output terminal for the connection of a semiconductor switching element, a capacitive charge storage configuration, which is coupled to the output terminal, a charging and discharging circuit having at least one input for feeding in at least one drive signal and an output connected to the capacitive charge storage configuration, and a discharging circuit with a connecting terminal. The connecting terminal is connected to the capacitive charge storage configuration and provides a discharging current for the charge storage configuration. A charging current or a discharging current for the capacitive charge storage configuration is available at the output depending on the drive signal. A method for driving the semiconductor switching element is also provided.

摘要翻译： 用于驱动半导体开关元件的电路配置包括用于连接半导体开关元件的输出端子，耦合到输出端子的电容性电荷存储配置，具有至少一个输入的充电和放电电路，用于馈入 至少一个驱动信号和连接到电容性电荷存储配置的输出，以及具有连接端子的放电电路。 连接端子连接到电容性电荷存储配置，并提供用于电荷存储配置的放电电流。 电容性电荷存储配置的充电电流或放电电流根据驱动信号在输出端可用。 还提供了用于驱动半导体开关元件的方法。

公开(公告)号：US4339668A

公开(公告)日：1982-07-13

申请号：US75679

申请日：1979-09-14

申请人： Ruediger Mueller ,  Michael Pomper ,  Ludwig Leipold

发明人： Ruediger Mueller ,  Michael Pomper ,  Ludwig Leipold

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/12 ,  H01L27/13 ,  H01L29/78 ,  H01L29/786 ,  H01P1/203 ,  H01P5/02

CPC分类号： H01P5/02 ,  H01L27/13 ,  Y10S331/03

摘要： A system is disclosed for coupling electrically isolated circuits in a monolithic integrated circuit. A signal coupler is integrated on a chip together with a primary circuit and a secondary circuit which is to be coupled to the primary circuit. The signal coupler comprises an integrated coupling capacitor which consists of a coplanar conductor path arrangement embedded into a passivation layer, the passivation layer being applied to an insulating substrate, preferably sapphire.

摘要翻译： 公开了用于在单片集成电路中耦合电隔离电路的系统。 信号耦合器与主电路和要与第一电路耦合的次级电路一起集成在芯片上。 信号耦合器包括集成耦合电容器，其由嵌入钝化层的共面导体路径布置组成，钝化层被施加到绝缘基板，优选蓝宝石。

公开(公告)号：US5086364A

公开(公告)日：1992-02-04

申请号：US657291

申请日：1991-02-19

申请人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi ,  Roland Weber

发明人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi ,  Roland Weber

IPC分类号： G01R31/02 ,  H03K17/082

CPC分类号： H03K17/0822 ,  G01R31/025

摘要： The voltage (U.sub.DS) on a power MOSFET (1) is compared with a voltage (U.sub.V) derived from the sum of the voltages of a Zener diode (3) and the threshold voltage (U.sub.T) of a second MOSFET (5) to detect a short circuit in a load (2) in series with the power MOSFET (1). When this total voltage is exceeded, the second MOSFET conducts. Its load current is then evaluated as the short circuit signal.

摘要翻译： 功率MOSFET（1）上的电压（UDS）与从齐纳二极管（3）的电压和第二MOSFET（5）的阈值电压（UT）之和导出的电压（UV）进行比较，以检测 与功率MOSFET（1）串联的负载（2）中的短路。 当超过该总电压时，第二个MOSFET导通。 然后将其负载电流评估为短路信号。

公开(公告)号：US4947234A

公开(公告)日：1990-08-07

申请号：US99577

申请日：1987-09-22

申请人： Josef Einzinger ,  Ludwig Leipold ,  Jeno Tihanyi ,  Roland Weber

发明人： Josef Einzinger ,  Ludwig Leipold ,  Jeno Tihanyi ,  Roland Weber

IPC分类号： H01L25/07 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H01L29/78

CPC分类号： H01L25/16 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01014 ,  H01L2924/01068 ,  H01L2924/13091

摘要： A semiconductor component with a power MOSFET and control circuit for controlling the power MOSFET. Both the power MOSFET and the control circuit have separate semiconductor bodies. The semiconductor body of the control circuit is arranged on one of the main surfaces of the semiconductor body of the power MOSFET. The control circuit is electrically insulated from the MOSFET by an insulating layer and mechanically coupled to the MOSFET by means of a bonding layer. The MOSFET is fastened to a cooling body which serves as a heat sink for the semiconductor component. The terminals of the control circuit and the MOSFET are attached to housing connections with leads.

摘要翻译： 具有功率MOSFET的半导体元件和用于控制功率MOSFET的控制电路。 功率MOSFET和控制电路都具有分离的半导体主体。 控制电路的半导体本体设置在功率MOSFET的半导体本体的主表面之一上。 控制电路通过绝缘层与MOSFET电绝缘，并通过结合层机械耦合到MOSFET。 MOSFET被固定到用作半导体部件的散热器的冷却体。 控制电路和MOSFET的端子与引线连接到外壳连接。

公开(公告)号：US4633292A

公开(公告)日：1986-12-30

申请号：US828575

申请日：1986-02-10

申请人： Christine Fellinger ,  Ludwig Leipold ,  Jeno Tihanyi

发明人： Christine Fellinger ,  Ludwig Leipold ,  Jeno Tihanyi

IPC分类号： H01L29/41 ,  H01L21/331 ,  H01L29/06 ,  H01L29/40 ,  H01L29/73 ,  H01L29/78 ,  H01L29/861

CPC分类号： H01L29/404 ,  H01L29/7802

摘要： Planar semiconductor component which has a substrate of one conduction type, and a contact-connected zone of opposite conductivity type embedded in the surface of the substrate in planar fashion and having a part thereof emerging to the surface. It also has a control electrode covering that part of the contact-connected contacted zone which emerges to the surface, an insulating layer on the surface, an edge electrode seated on the insulating layer at the edge of the substrate and electrically connected to the substrate, and at least one protective ring zone of the opposite conductivity type positioned between the edge of the substrate and the contact-connected zone and embedded in planar fashion in the surface. The ring zone includes at least one conducting layer completely covering a part of the substrate emerging to the surface between the protective ring zone and the contacted zone, wherein the conducting layer is electrically insulated from the emerging part of the substrate, and electrically contacted by one of the contact-connected protective ring zones embedded in planar fashion in the substrate surface.

摘要翻译： 平面半导体部件具有一个导电型的衬底和相对导电类型的接触连接区域，其以平面方式嵌入到衬底的表面中，并且其一部分露出到表面。 它还具有一个控制电极，其覆盖出现在表面上的接触接触区域的一部分，表面上的绝缘层，位于衬底边缘处的绝缘层上的边缘电极，并电连接到衬底， 以及位于基板的边缘和接触连接区域之间的相反导电类型的至少一个保护环区域，并且以平面方式嵌入在表面中。 环区包括至少一个导电层，其完全覆盖出现在保护环区域和接触区域之间的表面的衬底的一部分，其中导电层与衬底的出现部分电绝缘，并与一个电接触 的接触连接的保护环区域以平面方式嵌入衬底表面。

公开(公告)号：US5434521A

公开(公告)日：1995-07-18

申请号：US978637

申请日：1992-11-19

申请人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi

发明人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi

IPC分类号： G01R19/165 ,  H03K5/08 ,  H03K17/30 ,  H03K17/687 ,  H03K5/153

CPC分类号： H03K17/6872 ,  G01R19/16519 ,  H03K17/302

摘要： An integrated comparator circuit includes two complementary MOSFETs having main current paths being connected together in a series circuit at a connecting point. An inverter stage has two complementary MOSFETs with gate terminals connected to the connecting point. First, second and third terminals are provided. The first and second terminals are for an operating voltage, and the second and third terminals are for a voltage to be compared. The series circuit is connected between the first and third terminals, and the inverter stage is connected between the first and second terminals. One of the MOSFETs of the series circuit connected to the first terminal and one of the MOSFETs of the inverter stage connected to the first terminal are of the same channel type. The other of the MOSFETs of the series circuit connected to the third terminal and the other of the MOSFETs of the inverter stage connected the second terminal are of the same channel type.

摘要翻译： 集成比较器电路包括两个互补MOSFET，其中主电流路径在连接点处串联在一起连接在一起。 反相器级具有两个互补MOSFET，栅极端子连接到连接点。 首先，提供第二和第三终端。 第一和第二端子用于工作电压，第二和第三端子用于比较电压。 串联电路连接在第一和第三端子之间，变频器级连接在第一和第二端子之间。 连接到第一端子的串联电路的MOSFET之一和连接到第一端子的反相器级的MOSFET之一具有相同的通道类型。 连接到第三端子的串联电路的另一个MOSFET和连接到第二端子的反相器级的另一个MOSFET具有相同的通道类型。

公开(公告)号：US5371418A

公开(公告)日：1994-12-06

申请号：US95197

申请日：1993-07-23

申请人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi

发明人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi

IPC分类号： H01L27/088 ,  H03K17/00 ,  H03K17/06 ,  H03K17/687

CPC分类号： H03K17/6877 ,  H01L27/0883 ,  H03K17/063 ,  H03K2217/0036

摘要： Power FETs having a load at the source side require a gate voltage lying above the drain voltage in order to be driven completely conductive. This can occur with a known pump circuit. In the drive circuit disclosed, the diode connected to the gate terminal of the power FET is a depletion FET whose substrate terminal is applied to the oscillating voltage that is required for the operation of the pump circuit. The cut off voltage is thus synchronously set relative to the oscillating voltage such that low losses arise when loading C.sub.GS and an adequately high inhibit voltage can be built up when loading the pump capacitor.

摘要翻译： 在源极处具有负载的功率FET需要位于漏极电压之上的栅极电压，以便被驱动完全导电。 这可以用已知的泵电路进行。 在所公开的驱动电路中，连接到功率FET的栅极端子的二极管是耗尽FET，其基极端子被施加到泵电路的操作所需的振荡电压。 因此，截止电压相对于振荡电压被同步设定，使得当加载CGS时产生低损耗，并且当加载泵电容器时可以建立足够高的抑制电压。