摘要:
The power required to search a content addressable memory (CAM) is substantially reduced by forming the CAM to have a number of CAM banks with a corresponding number of power switches that control power to the CAM banks, and then controlling the power to search the CAM banks one at a time.
摘要:
The power required to search a content addressable memory (CAM) is substantially reduced by forming the CAM to have a number of CAM banks with a corresponding number of power switches that control power to the CAM banks, and then controlling the power to search the CAM banks one at a time.
摘要:
A low-cost, high-speed, bus-based communication system is provided that includes a master electronics card, a number of slave electronics cards, and a backplane that interconnects the master and the slave electronics cards via a serial bus, a parallel bus and some common signals for clocking and synchronization.
摘要:
Access to a bus is granted to one of a number of requesting communication circuits that each submitted a bus control request during a request period of an arbitration period in response to grant information which can be stored in a primary and a backup priority table. If a requesting communication circuit has an identity and priority that match the identity and priority of a communication circuit stored in a row of the primary or backup priority table that corresponds with the arbitration period, and the identities stored in the tables match only one requesting communication circuit, access to the bus is granted to the requesting communication circuit.
摘要:
Access to a bus is granted to one of a number of requesting communication circuits that each submitted a bus control request during a request period of an arbitration period in response to the entries in a priority table. If a requesting communication circuit has an identity and priority that match the identity and priority of a communication circuit stored in a row of the priority table that corresponds with the arbitration period, access to the bus is granted to the requesting communication circuit.
摘要:
The bus circuit of a master electronics card in a backplane-based communications system adaptively grants the upstream bus to the slave electronics cards by the early termination of a scheduled number of grants to a slave electronics card when the bus circuit on the master electronics card detects idle cells.
摘要:
An input memory circuit, which has a plurality of addresses that have an associated plurality of keys, forwarding information, and enable/disable flags, receives a plurality of input cells, extracts key information from each input cell, compares the key information from each input cell with the keys, and outputs forwarding information for an input cell when the key information of the input cell matches a key at an address and the address is enabled.
摘要:
Access to a bus is granted to one of a number of requesting communication circuits that each submitted a bus control request during a request period of an arbitration period in response to the entries in a priority table. If a requesting communication circuit has an identity and priority that match the identity and priority of a communication circuit stored in a row of the priority table that corresponds with the arbitration period, access to the bus is granted to the requesting communication circuit.
摘要:
A scrambling operation is used to space apart the grants that a communication circuit receives during a period of time, such as 512 arbitration periods. An operator can enter the number of arbitration periods that a communication circuit is to receive in blocks of sequential logical address ranges. The logical addresses are then changed to physical addresses that are spaced apart, thereby significantly reducing the buffering required by the communication circuit.
摘要:
Access to a bus is granted to one of a number of requesting communication circuits that each submitted a bus control request during a request period of an arbitration period in response to the entries in a priority table. If a requesting communication circuit has an identity and priority that match the identity and priority of a communication circuit stored in a row of the priority table that corresponds with the arbitration period, access to the bus is granted to the requesting communication circuit.