公开(公告)号：US08927370B2

公开(公告)日：2015-01-06

申请号：US11459416

申请日：2006-07-24

申请人： Chun-Yuan Lo ,  Chun-Pei Wu

发明人： Chun-Yuan Lo ,  Chun-Pei Wu

IPC分类号： H01L21/8234 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in the substrate adjacent to the sides of the first conductive layer. An inter-gate dielectric layer is then formed over the first conductive layer followed by forming a second conductive layer over the inter-gate dielectric layer. A transistor gate is subsequently formed over the gate insulating layer in the periphery area.

摘要翻译： 提供一种用于制造具有存储区域和周边区域的存储器的方法。 该方法包括在周边区域的基板上形成栅极绝缘层。 此后，在存储区域中形成第一导电层，随后在与第一导电层的侧面相邻的衬底中形成掩埋扩散区域。 然后在第一导电层之上形成栅极间电介质层，随后在栅极间电介质层上形成第二导电层。 随后在周边区域中的栅极绝缘层上形成晶体管栅极。

公开(公告)号：US20120247561A1

公开(公告)日：2012-10-04

申请号：US13306609

申请日：2011-11-29

申请人： Yun CHI ,  Cheng-Xuan Li ,  Shen-Han Yang ,  Hsin-Pei Wu ,  Kuan-Lin Wu ,  Chien-Wei Hsu ,  Shih-Han Chang

发明人： Yun CHI ,  Cheng-Xuan Li ,  Shen-Han Yang ,  Hsin-Pei Wu ,  Kuan-Lin Wu ,  Chien-Wei Hsu ,  Shih-Han Chang

IPC分类号： H01L51/46 ,  C07F15/00 ,  C07D401/14 ,  C07D409/14 ,  C07D495/04

CPC分类号： C07D401/14 ,  C07D409/14 ,  C07D495/04 ,  C07F15/0053 ,  H01G9/2031 ,  H01G9/2059 ,  H01L51/0037 ,  H01L51/0086 ,  Y02E10/542 ,  Y02E10/549

摘要： Disclosed is a 4,4′-dicarboxy-2,2′-bipyridine derived tridentate ligand represented by formula (I): wherein definitions of Y1, Y2, and R are the same as those defined in the specification. Also disclosed are a metal complex containing the aforesaid tridentate ligand and a dye-sensitized solar cell containing the metal complex.

摘要翻译： 公开了由式（I）表示的4,4'-二羧基-2,2'-联吡啶衍生的三齿配体：其中Y1，Y2和R的定义与说明书中定义的相同。 还公开了含有上述三齿配体的金属络合物和含有金属络合物的染料敏化太阳能电池。

公开(公告)号：US20070264774A1

公开(公告)日：2007-11-15

申请号：US11383073

申请日：2006-05-12

申请人： Tian-Shuan Luo ,  Chun-Pei Wu

发明人： Tian-Shuan Luo ,  Chun-Pei Wu

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A method of manufacturing a flash memory device having an enhanced gate coupling ratio includes steps of forming a first semiconductor layer on a substrate and forming a semiconductor spacer layer on top of the first semiconductor layer. The semiconductor spacer layer includes a plurality of recesses. The method provides a semiconductor spacer structure which functions to increase the contact area between a floating gate and a control gate of the flash memory device.

摘要翻译： 具有增强的栅极耦合比的闪存器件的制造方法包括在衬底上形成第一半导体层并在第一半导体层顶部形成半导体间隔层的步骤。 半导体间隔层包括多个凹部。 该方法提供半导体间隔结构，其用于增加闪存器件的浮动栅极和控制栅极之间的接触面积。

公开(公告)号：US20070259496A1

公开(公告)日：2007-11-08

申请号：US11417791

申请日：2006-05-03

申请人： Hsin-Fu Lin ,  Chun-Pei Wu

发明人： Hsin-Fu Lin ,  Chun-Pei Wu

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/76202 ,  H01L27/11521

摘要： A method for fabricating a non-volatile memory is provided. A dielectric layer, a first conductive layer, and a mask layer are formed sequentially on a substrate and then patterned to form a number of openings and floating gates. In addition, spacers are formed on the sidewalls of the openings. A source/drain region is formed in the substrate underneath each of the openings. A thermal process is performed to oxidize the substrate exposed by the opening to form an insulating layer above the source/drain region. Afterward, the mask layer is removed and an inter-gate dielectric layer is formed to cover the surface of the first conductive layer and the surface of the insulating layer. Subsequently, a second conductive layer is formed on the inter-gate dielectric layer.

摘要翻译： 提供了一种用于制造非易失性存储器的方法。 依次在基板上形成电介质层，第一导电层和掩模层，然后将其图案化以形成多个开口和浮动栅极。 此外，在开口的侧壁上形成间隔物。 源极/漏极区域形成在每个开口下方的衬底中。 进行热处理以氧化由开口暴露的衬底，以在源极/漏极区域上方形成绝缘层。 之后，去除掩模层，并形成栅极间电介质层以覆盖第一导电层的表面和绝缘层的表面。 随后，在栅极间电介质层上形成第二导电层。

公开(公告)号：US20060284267A1

公开(公告)日：2006-12-21

申请号：US11157303

申请日：2005-06-20

申请人： Hsin-Fu Lin ,  Chun-Pei Wu

发明人： Hsin-Fu Lin ,  Chun-Pei Wu

IPC分类号： H01L29/76 ,  H01L21/8236

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A flash memory comprises a substrate, control gates, doped regions, an isolation layer, isolation structures, floating gates, tunneling dielectric layers and inter-gate dielectric layers. The control gates are arranged over the substrate with a first direction, and the doped regions are arranged within the substrate with a second direction. The isolation layers are disposed between the control gates and the doping regions, and the isolation structures are disposed within the substrate where the doped regions and the control gates do not overlap. Furthermore, the floating gates are disposed between the control gates and the substrate that is not covered by the isolation layers. The tunneling dielectric layers are disposed between the substrate and the floating gates. The inter-gate dielectric layers are disposed between the control gates and the floating gates.

摘要翻译： 闪速存储器包括衬底，控制栅极，掺杂区域，隔离层，隔离结构，浮置栅极，隧道电介质层和栅极间电介质层。 控制栅极以第一方向布置在衬底上，并且掺杂区域以第二方向布置在衬底内。 隔离层设置在控制栅极和掺杂区域之间，并且隔离结构设置在衬底内，其中掺杂区域和控制栅极不重叠。 此外，浮动栅极设置在控制栅极和未被隔离层覆盖的衬底之间。 隧道电介质层设置在衬底和浮动栅极之间。 栅极间电介质层设置在控制栅极和浮栅之间。

公开(公告)号：US06337190B1

公开(公告)日：2002-01-08

申请号：US09466257

申请日：1999-12-17

申请人： Tzann-Shun Hwang ,  Szu-Pei Wu ,  Hsin-Hua Chou ,  Hwa-Yi Chen ,  Lung-Shen Lin ,  Hsin Tsai ,  Edward Chang

发明人： Tzann-Shun Hwang ,  Szu-Pei Wu ,  Hsin-Hua Chou ,  Hwa-Yi Chen ,  Lung-Shen Lin ,  Hsin Tsai ,  Edward Chang

IPC分类号： C12N900

CPC分类号： C12N9/1096 ,  C12P35/04

摘要： The present invention relates to mutant D-amino acid aminotransferase, including nucleic acids encoding mutant D-amino acid aminotransferase. The mutant D-amino acid aminotransferase of the present invention is obtained by the substitution of the glutamate residue at position 13 of wild type D-amino acid aminotransferase from Bacillus sphaericus with hydrophobic amino acids. The mutant D-amino acid aminotransferase can be used in the production of D-amino acid and the conversion of glutaryl-7-aminocephalosporanic acid from cephalosporin C. The present invention also includes replica-paper staining method for screening the cells expressing high DAT activity.

摘要翻译： 本发明涉及突变型D-氨基酸氨基转移酶，包括编码突变型D-氨基酸氨基转移酶的核酸。 通过用疏水性氨基酸取代来自球形芽孢杆菌的野生型D-氨基酸氨基转移酶的13位的谷氨酸残基获得本发明的突变型D-氨基酸氨基转移酶。 突变型D-氨基酸氨基转移酶可用于D-氨基酸的生产和戊二酰-7-氨基头孢菌酸从头孢菌素C的转化。本发明还包括用于筛选表达高DAT活性的细胞的复制纸染色方法 。

公开(公告)号：US20130082680A1

公开(公告)日：2013-04-04

申请号：US13481965

申请日：2012-05-29

申请人： TSUNG-PEI WU ,  XIAO-LIAN HE

发明人： TSUNG-PEI WU ,  XIAO-LIAN HE

IPC分类号： G01R31/00

CPC分类号： G01R31/001 ,  G01R1/04

摘要： An electrostatic discharge testing (ESD) apparatus includes a platform, a control unit, an ESD gun, an X rod, a Y rod, and a Z rod respectively parallel to designated XYZ axes of the platform. The Z rod is slidably disposed on the X rod via a first sliding joint, and the Y rod is slidably disposed on the Z rod via a second sliding joint. The ESD gun is disposed on the Y rod. The control unit controls the Z rod to slide along the X rod, and controls the Y rod to slide along the Z rod and along an axis of the Y rod, according to a predetermined testing program. Thus, the ESD gun is moved along a working path to test a product.

摘要翻译： 静电放电测试（ESD）装置包括分别平行于平台的指定XYZ轴的平台，控制单元，ESD枪，X杆，Y杆和Z杆。 Z杆通过第一滑动接头可滑动地设置在X杆上，并且Y杆通过第二滑动接头可滑动地设置在Z杆上。 防静电枪设置在Y杆上。 控制单元控制Z杆沿X杆滑动，并根据预定的测试程序控制Y杆沿Z杆和Y杆的轴线滑动。 因此，ESD枪沿着工作路径移动以测试产品。

公开(公告)号：US08300462B2

公开(公告)日：2012-10-30

申请号：US13367122

申请日：2012-02-06

申请人： Chun-Pei Wu ,  Chia-Ta Shieh ,  Chih-Wei Hung ,  Mars Chen

发明人： Chun-Pei Wu ,  Chia-Ta Shieh ,  Chih-Wei Hung ,  Mars Chen

IPC分类号： G11C16/04

CPC分类号： G11C16/0416 ,  G11C16/0433 ,  H01L27/11565 ,  H01L27/11568

摘要： A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage.

摘要翻译： 一种方法包括对电可擦除可编程只读存储器（EEPROM）阵列执行操作。 从程序操作和擦除操作中选择操作。 EEPROM阵列包括排列成行和列的EEPROM单元，以及沿列方向延伸的多个字线。 多个字线中的每一个连接到同一列中的EEPROM单元的控制栅极。 EEPROM阵列还包括沿行方向延伸的多个源极线。 多个源极线中的每一个连接到同一行中的EEPROM单元的源极。 在操作期间，多个源极线中的第一源极线被施加第一源极线电压，并且多个源极线中的第二源极线施加与第二源极线不同的第二源极线电压 第一源线电压。

公开(公告)号：US20120134209A1

公开(公告)日：2012-05-31

申请号：US13367122

申请日：2012-02-06

申请人： Chun-Pei Wu ,  Chia-Ta Shieh ,  Chih-Wei Hung ,  Mars Chen

发明人： Chun-Pei Wu ,  Chia-Ta Shieh ,  Chih-Wei Hung ,  Mars Chen

IPC分类号： G11C16/04

CPC分类号： G11C16/0416 ,  G11C16/0433 ,  H01L27/11565 ,  H01L27/11568

摘要： A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage.

摘要翻译： 一种方法包括对电可擦除可编程只读存储器（EEPROM）阵列执行操作。 从程序操作和擦除操作中选择操作。 EEPROM阵列包括排列成行和列的EEPROM单元，以及沿列方向延伸的多个字线。 多个字线中的每一个连接到同一列中的EEPROM单元的控制栅极。 EEPROM阵列还包括沿行方向延伸的多个源极线。 多个源极线中的每一个连接到同一行中的EEPROM单元的源极。 在操作期间，多个源极线中的第一源极线被施加第一源极线电压，并且多个源极线中的第二源极线施加与第二源极线不同的第二源极线电压 第一源线电压。

公开(公告)号：US08183106B2

公开(公告)日：2012-05-22

申请号：US11460216

申请日：2006-07-26

申请人： Kuan Fu Chen ,  Yin Jen Chen ,  Meng Hsuan Weng ,  Tzung Ting Han ,  Ming Shang Chen ,  Chun Pei Wu

发明人： Kuan Fu Chen ,  Yin Jen Chen ,  Meng Hsuan Weng ,  Tzung Ting Han ,  Ming Shang Chen ,  Chun Pei Wu

IPC分类号： H01L21/3205 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.

摘要翻译： 一种用于制造浮动栅极存储器件的方法包括使用自对准工艺在不需要附加光刻步骤的部分栅极结构上形成第四多晶硅层。 因此，可以实现增强的器件可靠性，因为可以以较低的栅极偏置电平保持更高的GCR。 此外，可以减少流程复杂性，从而增加吞吐量并减少设备故障。