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公开(公告)号：US5703532A
公开(公告)日：1997-12-30
申请号：US588218
申请日：1996-01-18
申请人： Hyun Jong Shin , Peter Hong Xiao
发明人： Hyun Jong Shin , Peter Hong Xiao
CPC分类号： H03F3/45219 , H03F3/265 , H03F3/3028 , H03F3/4565 , H03F3/45654 , H03F2203/45418 , H03F2203/45711
摘要： A self-biased, fully differential, complementary receiver apparatus and method is presented. The receiver accepts differential inputs that can vary over the full rail-to-rail common mode voltage range. It produces double-ended complementary outputs swinging rail-to-rail useful in signal level conversion and comparator applications. The receiver includes a dual, fully complementary and mirror-symmetrical arrangement of a differential input stage, a biasing stage and an output stage. A self biasing voltage is generated with a balanced voltage divider coupled between the outputs of the biasing stages. This frees both biasing outputs for use as analogous but complementary receiver outputs while providing the receiver with all the advantages of self bias. For small signal differential inputs, the input and biasing stages operate in their linear region useful for amplifier applications. Whereas the circuit is most advantageously implemented using both p-type and n-type CMOS transistors, it can similarly be advantageously implemented with bipolar transistors. Alternate circuit configurations are described.
摘要翻译： 提出了一种自偏置，全差分，互补的接收装置和方法。 接收器接受可在整个轨到轨共模电压范围内变化的差分输入。 它产生双端互补输出摆幅轨到轨可用于信号电平转换和比较器应用。 接收机包括差分输入级，偏置级和输出级的双重，完全互补和镜像对称的布置。 通过耦合在偏置级的输出端之间的平衡分压器产生自偏置电压。 这样就可以将两个偏置输出释放出来，作为类似但互补的接收器输出，同时为接收机提供自偏置的所有优点。 对于小信号差分输入，输入和偏置级在其对于放大器应用有用的线性区域中工作。 尽管电路最有利地使用p型和n型CMOS晶体管实现，但是也可以类似地利用双极型晶体管实现电路。 描述了备用电路配置。
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公开(公告)号：US06538695B1
公开(公告)日：2003-03-25
申请号：US09185796
申请日：1998-11-04
申请人： Peter Hong Xiao , Evan Y. Wang
发明人： Peter Hong Xiao , Evan Y. Wang
IPC分类号： H04N964
摘要： An on-chip FPN calibration method and circuits scheme applying a reference voltage signal to an array of calibration pixels coupled to a sensor matrix. Two data values are read from each bit line and used to calculate an offset and a gain error for a pixel column. A reference offset and a reference gain error value are then generated by computing the average offset and the average gain error from the collected offset and gain error values of each bit line. Calibration data for each bit line then comprises an offset difference and a gain error difference, the offset difference comprising the difference between the offset value for that bit line and the reference offset, and the gain error difference comprising the gain error difference between the gain error for that bit line and the reference gain error. The calibration data for each bit line is then stored in on-chip volatile memory and is used later under normal operation to compensate for the FPN effect.
摘要翻译： 片上FPN校准方法和将参考电压信号施加到耦合到传感器矩阵的校准像素阵列的电路方案。 从每个位线读取两个数据值，并用于计算像素列的偏移和增益误差。 然后通过从收集的每个位线的偏移和增益误差值计算平均偏移和平均增益误差来生成参考偏移和参考增益误差值。 然后，每个位线的校准数据包括偏移差和增益误差差，偏移差包括该位线的偏移值与参考偏移之间的差，以及包括增益误差之间的增益误差差的增益误差差 对于该位线和参考增益误差。 然后将每个位线的校准数据存储在片上易失性存储器中，并在正常操作下稍后使用以补偿FPN效应。
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公开(公告)号：US06275259B1
公开(公告)日：2001-08-14
申请号：US09017094
申请日：1998-02-02
申请人： Sudhir Muniswamy Gowda , Hyun Jong Shin , Hon-Sum Philip Wong , Peter Hong Xiao , Jungwook Yang
发明人： Sudhir Muniswamy Gowda , Hyun Jong Shin , Hon-Sum Philip Wong , Peter Hong Xiao , Jungwook Yang
IPC分类号： H04N5235
摘要： The present invention relates to an automatic gain control circuit in which the automatic gain control function is performed entirely in the digital domain. In an illustrative embodiment, the digital automatic gain control circuit for an image sensor having associated therewith an analog-to digital (A/D) converter for converting analog electrical signals from the image sensor to corresponding digital codes, includes a min/max detector for determining minimum and maximum electrical signal values from the digital codes of the A/D converter for each frame of image. A filter coupled to the min/max detector dampens instantaneous changes of the minimum and maximum values by filtering to provide filtered minimum and maximum values. A digital-to-analog (D/A) converter coupled to the filter generates minimum and maximum analog reference voltages corresponding to the respective minimum and maximum filtered values, the reference voltages being applied to the A/D converter to control associated amplitudes of the digital codes provided thereby.
摘要翻译： 本发明涉及自动增益控制电路，其中自动增益控制功能完全在数字域中执行。 在说明性实施例中，用于图像传感器的数字自动增益控制电路具有与图像传感器相关联的模数转换器（A / D），用于将来自图像传感器的模拟电信号转换成相应的数字代码，该最小/最大值检测器用于 根据每帧图像确定来自A / D转换器的数字代码的最小和最大电信号值。 耦合到最小/最大检测器的滤波器通过滤波来抑制最小值和最大值的瞬时变化，以提供滤波的最小值和最大值。 耦合到滤波器的数模（D / A）转换器产生对应于相应的最小和最大滤波值的最小和最大模拟参考电压，所述参考电压被施加到A / D转换器以控制相关幅度 由此提供数字代码。
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公开(公告)号：US6115066A
公开(公告)日：2000-09-05
申请号：US876694
申请日：1997-06-12
申请人： Sudhir Muniswamy Gowda , Hyun Jong Shin , Hon-Sum Philip Wong , Peter Hong Xiao , Jungwook Yang
发明人： Sudhir Muniswamy Gowda , Hyun Jong Shin , Hon-Sum Philip Wong , Peter Hong Xiao , Jungwook Yang
CPC分类号： H04N5/3575 , H04N5/374 , H04N5/3745 , H04N5/378
摘要： A CMOS image sensor is provided in which correlated double sampling is performed entirely in the digital domain. In an exemplary embodiment, the image sensor includes a plurality of imager cells arranged in rows and columns, where the imager cells of a particular column are coupled to a column data line of that column. Each active imager cell is capable of selectively providing a first output on an associated column data line indicative of a reset level during a first sampling interval. During a second sampling interval, each active imager cell provides a signal output on the associated column data line indicative of an amount of light incident upon that imager cell. At least one analog to digital (A/D) converter is coupled to the column data lines and converts the first and signal outputs on each column data line to first and second digital codes, respectively, to complete a correlated double sampling operation. The invention eliminates the need for analog capacitors to store the reset and signal levels.
摘要翻译： 提供了一种CMOS图像传感器，其中相关的双重采样完全在数字域中执行。 在示例性实施例中，图像传感器包括以行和列排列的多个成像器单元，其中特定列的成像器单元耦合到该列的列数据线。 每个有源成像器单元能够在指示在第一采样间隔期间的复位电平的相关联的列数据线上选择性地提供第一输出。 在第二采样间隔期间，每个有源成像器单元在相关联的列数据线上提供指示入射在该成像器单元上的光量的信号输出。 至少一个模数（A / D）转换器耦合到列数据线，并将每列列数据线上的第一和第一信号输出分别转换成第一和第二数字代码，以完成相关双重采样操作。 本发明消除了对模拟电容器存储复位和信号电平的需要。
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公开(公告)号：US5920274A
公开(公告)日：1999-07-06
申请号：US906595
申请日：1997-08-05
申请人： Sudhir Muniswamy Gowda , Hyun Jong Shin , Hon-Sum Philip Wong , Peter Hong Xiao , Jungwook Yang
发明人： Sudhir Muniswamy Gowda , Hyun Jong Shin , Hon-Sum Philip Wong , Peter Hong Xiao , Jungwook Yang
摘要： Disclosed is an image sensor having A/D conversion circuitry coupled to column data lines of an image sensor array. The A/D conversion circuitry digitizes analog signals on the column data lines, each representing intensity of light incident upon an active imager cell. Higher resolution is provided for darker light levels than for bright light levels, such that a high resolution image is obtained with less storage data than would otherwise be required. In one embodiment, the A/D conversion circuitry includes a plurality of comparators, each having a first input coupled to one or more column data lines and a second input coupled to receive a time-varying reference signal, and a plurality of n-bit counters coupled to the comparator outputs. An n-bit to m-bit converter nonlinearly maps n-bit codes to m-bit codes and provides the m-bit codes to an m-bit D/A converter which produces the time-varying reference signal. In another embodiment, the A/D conversion circuitry is comprised of a non-uniform successive approximation A/D converter.
摘要翻译： 公开了一种具有耦合到图像传感器阵列的列数据线的A / D转换电路的图像传感器。 A / D转换电路对列数据线上的模拟信号进行数字化，每个数据线表示入射到有源成像器单元上的光的强度。 提供更高的分辨率用于较暗的亮度级别，而不是明亮的亮度级别，这样获得的高分辨率图像的存储数据少于否则需要。 在一个实施例中，A / D转换电路包括多个比较器，每个比较器具有耦合到一个或多个列数据线的第一输入和耦合以接收时变参考信号的第二输入和多个n位 计数器耦合到比较器输出。 n位到m位转换器将n位代码非线性地映射到m位代码，并将m位代码提供给产生时变参考信号的m位D / A转换器。 在另一个实施例中，A / D转换电路由不均匀的逐次逼近A / D转换器组成。
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公开(公告)号：US5898168A
公开(公告)日：1999-04-27
申请号：US873610
申请日：1997-06-12
申请人： Sudhir Muniswamy Gowda , Hyun Jong Shin , Hon-Sum Philip Wong , Peter Hong Xiao , Jungwook Yang
发明人： Sudhir Muniswamy Gowda , Hyun Jong Shin , Hon-Sum Philip Wong , Peter Hong Xiao , Jungwook Yang
IPC分类号： H04N5/351 , H04N5/353 , H04N5/357 , H04N5/359 , H04N5/363 , H04N5/374 , H04N5/3745 , H04N5/378 , H04N3/14 , H04N5/335
CPC分类号： H04N5/3592 , H04N5/3532 , H04N5/3575 , H04N5/363 , H04N5/3745
摘要： Disclosed is an image sensing device having a reduced number of transistors within each imager cell as compared to prior art devices. Each imager cell includes a photosensitive element providing a photocharge responsive to incoming light, and first, second and third transistors. The first transistor is coupled to an activation line, e.g., a row select line, that carries an activation signal to a first plurality of imager cells to selectively activate cells for image data readout. This transistor transfers the photocharge towards a reference circuit node within the image cell in response to the activation signal. The second transistor is operably coupled to the first transistor, and is operative to selectively set a voltage level at the reference node. The third transistor has a control terminal coupled to the reference node, and an output terminal coupled to an output data bus common to a second plurality of image cells, e.g., a column of cells. The third transistor providing an output signal on the data line related to the reference node voltage, which is indicative of an amount of light incident upon the photosensitive element.
摘要翻译： 公开了一种与现有技术装置相比，每个成像器单元内的晶体管数量减少的图像感测装置。 每个成像器单元包括响应于入射光提供光电荷的光敏元件以及第一，第二和第三晶体管。 第一晶体管耦合到激活线，例如行选择线，其将激活信号传送到第一多个成像器单元，以选择性地激活用于图像数据读出的单元。 该晶体管响应于激活信号将光电荷转移到图像单元内的参考电路节点。 第二晶体管可操作地耦合到第一晶体管，并且可操作以选择性地设置参考节点处的电压电平。 第三晶体管具有耦合到参考节点的控制端子，以及耦合到第二多个图像单元（例如，单元格列）公共的输出数据总线的输出端子。 第三晶体管在与参考节点电压相关的数据线上提供输出信号，其指示入射到感光元件上的光量。
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公开(公告)号：US06344877B1
公开(公告)日：2002-02-05
申请号：US08873539
申请日：1997-06-12
申请人： Sudhir Muniswamy Gowda , Hyun Jong Shin , Hon-Sum Philip Wong , Peter Hong Xiao , Jungwook Yang
发明人： Sudhir Muniswamy Gowda , Hyun Jong Shin , Hon-Sum Philip Wong , Peter Hong Xiao , Jungwook Yang
IPC分类号： H04N964
CPC分类号： H04N5/3745 , H04N5/3575 , H04N5/361 , H04N5/3651
摘要： Disclosed is an image sensor including one or more dummy pixels that produce a reference signal which is used to compensate for errors within the devices of the main pixel cells. In one embodiment, at least one dummy pixel is used in conjunction with other circuitry to correct for nonlinearities in the transfer characteristic of a source follower transistor within each pixel. In another embodiment, an array of dummy pixels is used to correct for leakage current within the pixels during an electronic shutter mode of operation. The two techniques can be combined whereby both threshold voltage mismatch and leakage current are compensated for.
摘要翻译： 公开了一种图像传感器，其包括产生用于补偿主像素单元的装置内的误差的参考信号的一个或多个虚拟像素。 在一个实施例中，至少一个虚拟像素与其他电路结合使用，以校正每个像素内的源极跟随器晶体管的传输特性中的非线性。 在另一个实施例中，在电子快门操作模式期间，使用虚拟像素阵列来校正像素内的漏电流。 可以组合两种技术，由此补偿阈值电压失配和泄漏电流。
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公开(公告)号：US6137432A
公开(公告)日：2000-10-24
申请号：US187308
申请日：1998-11-04
申请人： Peter Hong Xiao
发明人： Peter Hong Xiao
摘要： A low-power column parallel ADC architecture for image sensors that reduces the power consumption by reducing the number of switchings of a comparator to digitize a row of pixel data. Two ramp reference signals are provided in accordance with the principles of this invention. A first ramp signal is provided to each comparator that is clocked with an associated first clock signal. In each column comparator, the first ramp signal is compared to the pixel data using clock1, wherein clock1 corresponds to N multiple of a second clock signal (clock2), with N>1. Only when the column comparator detects a first crossover with the first ramp signal, then the comparator switches at every clock cycle of the second clock, clock2, to compare and detect a second crossover point with the second reference signal. This arrangement can greatly reduce the number of switchings required to digitize a row of pixel data, thereby resulting in significant power saving.
摘要翻译： 用于图像传感器的低功耗列并行ADC架构，通过减少比较器的切换次数来数字化一行像素数据来降低功耗。 根据本发明的原理提供两个斜坡参考信号。 第一斜坡信号被提供给每个比较器，其被相关联的第一时钟信号计时。 在每列比较器中，使用clock1将第一斜坡信号与像素数据进行比较，其中clock1对应于第二时钟信号（clock2）的N倍，N> 1。 只有当列比较器检测到具有第一斜坡信号的第一个交叉时，比较器将在第二个时钟clock2的每个时钟周期切换，以便与第二个参考信号比较和检测第二个交叉点。 这种布置可以大大减少数字化一行像素数据所需的切换次数，从而导致显着的功率节省。
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公开(公告)号：US5877715A
公开(公告)日：1999-03-02
申请号：US873537
申请日：1997-06-12
申请人： Sudhir Muniswamy Gowda , Hyun Jong Shin , Hon-Sum Philip Wong , Peter Hong Xiao , Jungwook Yang
发明人： Sudhir Muniswamy Gowda , Hyun Jong Shin , Hon-Sum Philip Wong , Peter Hong Xiao , Jungwook Yang
CPC分类号： H03M1/1295 , H03M1/1023 , H03M1/123 , H04N3/155 , H03M1/56
摘要： Disclosed is a circuit for performing correlated double sampling entirely in the digital domain. In an exemplary embodiment, the circuit includes a plurality of comparators, each having a first input coupled to an associated data line for receiving first and second signals in first and second sampling intervals, respectively. A time varying reference signal is applied to the second input of each comparator. A plurality of up/down counters are coupled to respective ones of the comparators, and each is operable to count in a first direction during the first sampling interval and in an opposite direction during the second sampling interval. Each up/down counter is caused to stop counting when the amplitude of the variable reference signal substantially equals the amplitude of the respective first or second signal. As a result, each up/down counter provides an output representing a subtraction of one of said first or second signals from the other. The invention has particular utility when used in conjunction with a CMOS image sensor.
摘要翻译： 公开了一种完全在数字领域进行相关双重采样的电路。 在示例性实施例中，电路包括多个比较器，每个比较器具有耦合到相关联的数据线的第一输入，用于分别在第一和第二采样间隔中接收第一和第二信号。 时变参考信号被施加到每个比较器的第二输入端。 多个向上/向下计数器耦合到相应的比较器，并且每个可操作以在第一采样间隔期间以第一方向计数，并且在第二采样间隔期间以相反的方向计数。 当可变参考信号的幅度基本上等于相应的第一或第二信号的幅度时，使每个向上/向下计数器停止计数。 结果，每个向上/向下计数器提供表示从另一个减去所述第一或第二信号之一的输出。 当与CMOS图像传感器结合使用时，本发明具有特别的用途。
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