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公开(公告)号：US06775961B2
公开(公告)日：2004-08-17
申请号：US10112060
申请日：2002-04-01
IPC分类号： B65B1102
CPC分类号： B65B11/04 , B65B25/24 , B65B2011/002
摘要： A device for tensioning web, such as a plastics web dispensed from a shuttle in a wrapping machine, is disclosed. The wrapping machine usually includes an endless track positioned about an object to be wrapped and the shuttle travels on the endless track, dispensing the web as it goes. The rate at which web is dispensed varies as the shuttle progresses around the track and is dependent upon the shape of the track and the shape of the object to be wrapped. The web tensioning device attempts to maintain a constant tension in the web and includes a pair of rollers covered with resilient material. The rollers are urged together to form a nip with the resilient covering of the rollers compressed in the nip. The web is fed between the nip of the rollers.
摘要翻译： 公开了一种用于张紧卷筒纸的装置，例如由包装机中的梭子分配的塑料织物。 包装机通常包括围绕要包裹的物体定位的循环轨道，并且梭子在环形轨道上行进，当纸幅移动时分配纸幅。 卷材的分配速率随着梭子在轨道周围进行而变化，并且取决于轨道的形状和被包裹物体的形状。 卷筒纸张紧装置试图在卷筒纸中保持恒定的张力，并且包括用弹性材料覆盖的一对辊。 将辊压在一起以形成辊隙，辊隙中的辊的弹性覆盖物被压缩。 纸幅在辊的辊隙之间进给。
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公开(公告)号：US4097753A
公开(公告)日：1978-06-27
申请号：US673178
申请日：1976-04-02
CPC分类号： H03M1/1245
摘要： A comparator circuit for comparing two voltage levels in a C-2C A/D and D/A converter, comprising four cross-coupled active devices (FETs) in a latch arrangement whereby an offset voltage is used to compensate for imbalances in the comparator. The comparator includes a first FET having its gate electrode connected to the output of the D/A converter, and a second FET having its gate electrode connected to an analog input voltage. The first and second FETs each have one of their electrodes connected to a common voltage source. A third and a fourth FET have one of their electrodes connected respectively to the other electrode of the first and second FETs at first and second common nodes, respectively. The output of the comparator is provided at one of such first and second common nodes. The first and second nodes are also respectively connected to the gate electrodes of the fourth and third FETs in a cross-coupled arrangement. The other electrode of both the third and fourth FETs are connected to a common phase voltage source. An offset voltage is generated at the input to either of the gate electrodes of the first and second FETs to set the comparator at a balance point and thereby compensate for the differences in the threshold voltages and current carrying capabilities of the four FETs. Also, the comparator has relatively high input impedance, gain and bandwidth.
摘要翻译： 一种用于比较C-2C A / D和D / A转换器中的两个电压电平的比较器电路，其包括锁存装置中的四个交叉耦合有源器件（FET），由此使用偏移电压来补偿比较器中的不平衡。 比较器包括其栅电极连接到D / A转换器的输出的第一FET，以及其栅电极连接到模拟输入电压的第二FET。 第一和第二FET各自具有连接到公共电压源的电极中的一个。 第三和第四FET分别具有在第一和第二公共节点分别连接到第一和第二FET的另一个电极的一个电极。 比较器的输出被提供在这样的第一和第二公共节点之一处。 第一和第二节点也以交叉耦合的方式分别连接到第四和第三FET的栅电极。 第三和第三FET的另一个电极连接到公共相电压源。 在第一和第二FET的栅电极的输入处产生偏移电压，以将比较器设置在平衡点，从而补偿四个FET的阈值电压和载流能力的差异。 此外，比较器具有相对较高的输入阻抗，增益和带宽。
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公开(公告)号：US06182233B2
公开(公告)日：2001-01-30
申请号：US09196985
申请日：1998-11-20
IPC分类号： G06F112
CPC分类号： G06F9/3869
摘要： An interlocked pipelined CMOS (IPCMOS) family of logic circuits provides extremely high performance pipelined operation and guarantees error free operation where variations in timing are compensated for automatically by the circuits. The IPCMOS logic circuits also provide a standard interface that makes it possible to interface different macro types easily. The IPCMOS logic circuits feature interlocking in both the forward and reverse directions. This “handshaking” guarantees error free timing and makes it possible to eliminate the need for a global clock at the macro level. Timing signals are generated locally at the macro level from the handshaking signals between macros. This makes it possible for the local circuits to deal with global timing variations caused by power supply noise, ACLV, and parameter variations. The macros operate in a pipelined mode with data advancing automatically from macro to macro with the timing controlled by the local handshaking signals. This pipelined operation results in an extremely fast cycle time. Another feature of IPCMOS is that the data inputs to a macro are only sampled when the data is in a valid state. making the concept of a standard macro interface possible. With this standard interface, different logic types such as static and dynamic circuits can be easily interconnected and the concept of reusable macros becomes a reality.
摘要翻译： 联锁流水线CMOS（IPCMOS）逻辑电路系列提供极高性能的流水线操作，并保证无错误运行，其中时序的变化由电路自动补偿。 IPCMOS逻辑电路还提供了一个标准接口，可以轻松地接口不同的宏类型。 IPCMOS逻辑电路在正向和反向方向均互锁。 这种“握手”保证了无错误的定时，并且可以消除在宏观级别对全局时钟的需要。 定时信号是从宏之间的握手信号在宏观级别本地生成的。 这使得本地电路可以处理由电源噪声，ACLV和参数变化引起的全局时序变化。 宏以流水线模式运行，数据由宏到宏自动提前，由本地握手信号控制。 这种流水线操作导致极快的循环时间。 IPCMOS的另一个特点是仅当数据处于有效状态时才对宏进行数据输入。 使得标准宏接口的概念成为可能。 使用这种标准接口，可以轻松地将不同的逻辑类型（如静态和动态电路）互连起来，并且可重用宏的概念成为现实。
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4.发明授权Asynchronous pipeline control interface using tag values to control passing data through successive pipeline stages 失效异步管道控制接口使用标签值来控制通过连续流水线阶段的传递数据公开(公告)号：US06925549B2
公开(公告)日：2005-08-02
申请号：US09746647
申请日：2000-12-21
申请人： Peter William Cook , Andrew Douglas Davies , Stanley Everett Schuster , Daniel Lawrence Stasiak
发明人： Peter William Cook , Andrew Douglas Davies , Stanley Everett Schuster , Daniel Lawrence Stasiak
CPC分类号： G06F7/00 , G06F9/3871 , G06F2207/3864
摘要： An apparatus and method for externally managing data within an asynchronous pipeline. The asynchronous pipeline over which control is sought includes a data path and a control path. In accordance with the method of the present invention, a data tag value is assigned to the data prior to its entry into the asynchronous pipeline. The data tag value is sent into the control path at the same time the data is sent into its data path such that the data tag value passes through the asynchronous pipeline in parallel with the data to which it is assigned. At a given stage within the asynchronous pipeline, the data tag value is compared with a control tag value, and only in response to the data tag value matching the control tag value is the data permitted to pass to the next stage within the asynchronous pipeline.
摘要翻译： 一种在异步流水线外部管理数据的装置和方法。 寻求控制的异步流水线包括数据路径和控制路径。 根据本发明的方法，数据标签值在其进入异步流水线之前被分配给数据。 在将数据发送到其数据路径的同时，将数据标签值发送到控制路径，使得数据标签值与其被分配的数据并行地通过异步流水线。 在异步管道中的给定阶段，将数据标签值与控制标签值进行比较，只有响应于匹配控制标签值的数据标签值才允许传递到异步管道中的下一级。
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公开(公告)号：US4028694A
公开(公告)日：1977-06-07
申请号：US585629
申请日：1975-06-10
CPC分类号： H01L27/0805 , H03M1/78 , H03M1/802
摘要： A C-2C analog-to digital and digital-to-analog converter is described, the C-2C designation referring to the arrangement of capacitance in a capacitor ladder network. The capacitors are formed in a monolithic, multilayer structure which includes a substrate, diffusion regions in the substrate, a polysilicon layer and an aluminum layer wherein the capacitances are formed between the aluminum layer and the polysilicon layer and between the polysilicon layer and the diffusion region, and these capacitances have the ratio of 2C to C respectively. The capacitor ladder network formed in the multilayer structure can be trimmed or adjusted electrically after manufacture to obtain the desired tolerances.
摘要翻译： 描述了C-2C模拟到数字和数模转换器，C-2C指定是指电容梯形网络中电容的布置。 电容器形成为单片多层结构，其包括衬底，衬底中的扩散区，多晶硅层和铝层，其中电容在铝层和多晶硅层之间以及多晶硅层和扩散区之间形成 ，这些电容分别具有2C与C的比例。 在多层结构中形成的电容梯形网络可以在制造之后进行电动修整或调整以获得所需的公差。
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6.发明授权公开(公告)号：US06946869B2
公开(公告)日：2005-09-20
申请号：US10685863
申请日：2003-10-15
申请人： Hans M. Jacobson , Pradip Bose , Alper Buyuktosunoglu , Peter William Cook , Philip George Emma , Prabhakar N. Kudva , Stanley Everett Schuster
发明人： Hans M. Jacobson , Pradip Bose , Alper Buyuktosunoglu , Peter William Cook , Philip George Emma , Prabhakar N. Kudva , Stanley Everett Schuster
CPC分类号： H03K19/0016
摘要： Leakage current control devices include a circuit having one or more functions in a data path where the functions are executed in a sequence. Each of the functions has power reduction logic to energize each respective function. A leakage control circuit interacts with the power reduction logic, so that the functions are energized or deenergized in a control sequence such that the functions where the data is resident are energized and at least one of the other functions is not energized.
摘要翻译： 泄漏电流控制装置包括在序列中执行功能的数据路径中具有一个或多个功能的电路。 每个功能具有功率降低逻辑以激励每个相应的功能。 泄漏控制电路与功率降低逻辑相互作用，使得功能在控制序列中被激励或断电，使得数据驻留的功能被激励，并且其他功能中的至少一个没有通电。
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公开(公告)号：US6006025A
公开(公告)日：1999-12-21
申请号：US934995
申请日：1997-09-22
CPC分类号： G06F17/5077 , G06F1/10 , G06F2217/62
摘要： A method of wire routing includes the steps of providing an array of cells on a semiconductor chip, determining a minimum distance location between a first clock point, an second clock point and a drive point for connecting to a connection point in the array of cells, and defining a wire path through an array of blockages disposed in the array of cells from the minimum distance location to the first clock point and from the minimum distance location to the second clock point to create a path for a wire for connecting the first clock point and the second clock point to a connection point such that skew is minimized between the starting clock point and the second clock point from the connection point when a clock signal is provided to the connection point from the drive point.
摘要翻译： 线路布线方法包括以下步骤：在半导体芯片上提供单元阵列，确定第一时钟点，第二时钟点和连接到单元阵列中的连接点的驱动点之间的最小距离位置， 以及通过设置在所述小区阵列中的阻塞阵列从所述最小距离位置到所述第一时钟点以及从所述最小距离位置到所述第二时钟点来定义有线路径，以创建用于连接所述第一时钟点的线路的路径 并且第二时钟点指向连接点，使得当从驱动点向连接点提供时钟信号时，从连接点开始时钟点和第二时钟点之间的偏移最小化。
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