公开(公告)号：US06960523B2

公开(公告)日：2005-11-01

申请号：US10406645

申请日：2003-04-03

Applicant: Michael Maldei ,  Prakash C. Dev ,  David Dobuzinsky ,  Johnathan Faltermeier ,  Thomas S. Rupp ,  Chienfan Yu ,  Rajesh Rengarajan ,  John Benedict ,  Munir-ud-Din Naeem

Inventor： Michael Maldei ,  Prakash C. Dev ,  David Dobuzinsky ,  Johnathan Faltermeier ,  Thomas S. Rupp ,  Chienfan Yu ,  Rajesh Rengarajan ,  John Benedict ,  Munir-ud-Din Naeem

IPC: H01L21/311 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/4763 ,  H01L21/3205

CPC classification number: H01L27/10888 ,  H01L21/31116 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.

Abstract translation: 相对于氮化物盖层的蚀刻速率，氮化物衬垫层的蚀刻速率得以改善。 氮化物衬垫层位于衬底附近的位于衬底顶部的堆叠结构的暴露部分。 氮化物覆盖层位于堆叠结构的顶部。 沿堆叠结构的侧壁形成氧化物间隔物。 氮化物衬里层被图案化和蚀刻以在衬底中形成至少一个开口，而氮化物覆盖层基本保持不变。

公开(公告)号：US06620699B2

公开(公告)日：2003-09-16

申请号：US09967226

申请日：2001-09-28

Applicant: Arnd Scholz ,  Prakash C. Dev

Inventor： Arnd Scholz ,  Prakash C. Dev

IPC: H01L2120

CPC classification number: H01L27/10876 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10891 ,  H01L29/66181

Abstract: A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes depositing an oxide liner in a trench etched from a semiconductor material, wherein the oxide lines abuts a pad nitride layer, a pad oxide layer under the pad nitride layer, and a recessed gate poly in the trench. The method further includes depositing a spacer material on the oxide liner, removing exposed portions of the oxide layer from the semiconductor, and depositing a poly stud material over the semiconductor wherein the spacer material is encapsulated in poly stud material. The method includes polishing the semiconductor to the top trench oxide layer, and etching the top trench oxide layer.

Abstract translation: 提供了一种用于在深沟槽器件DRAM单元中形成内部氮化物间隔物的方法。 该方法包括在从半导体材料蚀刻的沟槽中沉积氧化物衬垫，其中氧化物线邻接衬垫氮化物层，在衬垫氮化物层下方的衬垫氧化物层和沟槽中的凹陷栅极聚合物。 该方法还包括在氧化物衬垫上沉积间隔物材料，从半导体去除氧化物层的暴露部分，以及在半导体上沉积多晶硅柱材料，其中间隔物材料被包封在聚晶材料中。 该方法包括将半导体抛光到顶部沟槽氧化物层，并蚀刻顶部沟槽氧化物层。