公开(公告)号：US20050051839A1

公开(公告)日：2005-03-10

申请号：US10655199

申请日：2003-09-04

Applicant: Johnathan Faltermeier ,  Jeremy Stephens ,  David Dobuzinsky ,  Larry Clevenger ,  Munir Naeem ,  Chienfan Yu ,  Larry Nesbit ,  Rama Divakaruni ,  Michael Maldei

Inventor： Johnathan Faltermeier ,  Jeremy Stephens ,  David Dobuzinsky ,  Larry Clevenger ,  Munir Naeem ,  Chienfan Yu ,  Larry Nesbit ,  Rama Divakaruni ,  Michael Maldei

IPC: H01L21/60 ,  H01L21/8242 ,  H01L29/76

CPC classification number: H01L27/10888 ,  H01L21/76897 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10891

Abstract: A method of forming borderless contacts and a borderless contact structure for semiconductor devices. A preferred embodiment comprises using a second etch selectivity material disposed over a first etch selectivity material to preserve the first etch selectivity material during the etch processes for the various material layers of the semiconductor device while forming the borderless contacts.

Abstract translation: 形成无边界接触的方法和用于半导体器件的无边界接触结构。 优选实施例包括使用设置在第一蚀刻选择性材料上的第二蚀刻选择性材料，以在半导体器件的各种材料层的蚀刻工艺期间保持第一蚀刻选择性材料，同时形成无边界接触。

公开(公告)号：US20090228624A1

公开(公告)日：2009-09-10

申请号：US12045369

申请日：2008-03-10

Applicant: Michael Maldei ,  Petra Stumm

Inventor： Michael Maldei ,  Petra Stumm

IPC: G06F13/00

CPC classification number: G06F13/4217 ,  Y02D10/14 ,  Y02D10/151

Abstract: Embodiments of the invention are related to methods, systems, and articles of manufacture for transferring data between two devices using an interconnect bus. On each conductive line of the bus, a bit representing a first logic state is transferred if a current bit is the same as an immediately previously transmitted bit. If the current bit is different from the immediately previously transmitted bit, then a bit representing a second logic state is transferred.

Abstract translation: 本发明的实施例涉及使用互连总线在两个设备之间传送数据的方法，系统和制品。 在总线的每个导线上，如果当前位与之前发送的位相同，则传送表示第一逻辑状态的位。 如果当前位不同于紧接在先发送的位，则传送表示第二逻辑状态的位。

公开(公告)号：US20050077562A1

公开(公告)日：2005-04-14

申请号：US10605590

申请日：2003-10-10

Applicant: Rama Divakaruni ,  Johnathan Faltermeier ,  Michael Maldei ,  Jay Strane

Inventor： Rama Divakaruni ,  Johnathan Faltermeier ,  Michael Maldei ,  Jay Strane

IPC: H01L21/60 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L21/76897 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.

Abstract translation: 提供一种形成集成电路的存储单元阵列的位线的方法和将存储单元阵列外部的外部区域的晶体管互连的导线。 该方法包括根据第一临界尺寸掩模在覆盖存储单元阵列的电介质区域中图形化槽。 在槽中形成与基板和位线的位线接触。 此后，形成导线，其基本上由选自金属的金属和由第二关键尺寸掩模图案化的水平定向图案中的金属导电化合物组成的组中的至少一种材料组成，其中导线将位线互连到外部电路的晶体管 在存储单元阵列外部，导线仅在存储单元阵列的外围边缘处互连到位线。

公开(公告)号：US07049193B2

公开(公告)日：2006-05-23

申请号：US10960735

申请日：2004-10-07

Applicant: Michael Maldei ,  Jinhwan Lee ,  Guenter Gerstmeier ,  Brian Cousineau ,  Jon S. Berry, II ,  Steven M. Baker ,  Malati Hedge

Inventor： Michael Maldei ,  Jinhwan Lee ,  Guenter Gerstmeier ,  Brian Cousineau ,  Jon S. Berry, II ,  Steven M. Baker ,  Malati Hedge

IPC: H01L21/8244

CPC classification number: H01L27/1052 ,  H01L21/3185 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894

Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.

Abstract translation: 一种制造半导体结构的方法，其中半导体结构包括芯区域和周边区域。 芯区域包括多个晶体管，并且周边区域包括多个晶体管。 该方法包括使用覆盖半导体结构的等离子体增强化学气相沉积来沉积中间线衬里。 通过使用等离子体增强化学气相沉积，可以根据核心区域和外围区域中的晶体管之间的距离来控制沉积在芯区域和外围区域中的MOL衬垫的量。

公开(公告)号：US06960523B2

公开(公告)日：2005-11-01

申请号：US10406645

申请日：2003-04-03

Applicant: Michael Maldei ,  Prakash C. Dev ,  David Dobuzinsky ,  Johnathan Faltermeier ,  Thomas S. Rupp ,  Chienfan Yu ,  Rajesh Rengarajan ,  John Benedict ,  Munir-ud-Din Naeem

Inventor： Michael Maldei ,  Prakash C. Dev ,  David Dobuzinsky ,  Johnathan Faltermeier ,  Thomas S. Rupp ,  Chienfan Yu ,  Rajesh Rengarajan ,  John Benedict ,  Munir-ud-Din Naeem

IPC: H01L21/311 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/4763 ,  H01L21/3205

CPC classification number: H01L27/10888 ,  H01L21/31116 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.

Abstract translation: 相对于氮化物盖层的蚀刻速率，氮化物衬垫层的蚀刻速率得以改善。 氮化物衬垫层位于衬底附近的位于衬底顶部的堆叠结构的暴露部分。 氮化物覆盖层位于堆叠结构的顶部。 沿堆叠结构的侧壁形成氧化物间隔物。 氮化物衬里层被图案化和蚀刻以在衬底中形成至少一个开口，而氮化物覆盖层基本保持不变。

公开(公告)号：US06870211B1

公开(公告)日：2005-03-22

申请号：US10605590

申请日：2003-10-10

Applicant: Rama Divakaruni ,  Johnathan E. Faltermeier ,  Michael Maldei ,  Jay Strane

Inventor： Rama Divakaruni ,  Johnathan E. Faltermeier ,  Michael Maldei ,  Jay Strane

IPC: H01L21/60 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L21/76897 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.

Abstract translation: 提供一种形成集成电路的存储单元阵列的位线的方法和将存储单元阵列外部的外部区域的晶体管互连的导线。 该方法包括根据第一临界尺寸掩模在覆盖存储单元阵列的电介质区域中图形化槽。 在槽中形成与基板和位线的位线接触。 此后，形成导线，其基本上由选自金属的金属和由第二关键尺寸掩模图案化的水平定向图案中的金属导电化合物组成的组中的至少一种材料组成，其中导线将位线互连到外部电路的晶体管 在存储单元阵列外部，导线仅在存储单元阵列的外围边缘处互连到位线。

公开(公告)号：US5562781A

公开(公告)日：1996-10-08

申请号：US374962

申请日：1995-01-19

Applicant: David C. Ingram ,  Michael Maldei

Inventor： David C. Ingram ,  Michael Maldei

IPC: H01L31/0376 ,  H01L31/076 ,  H01L31/06 ,  H01L31/068 ,  H01L31/07 ,  H01L31/075 ,  H01L31/20

CPC classification number: H01L31/076 ,  H01L31/03762 ,  Y02E10/548

Abstract: A photovoltaic cell comprising a plurality of film layers, at least one of the layers being a semiconductor film of amorphous, hydrogenated carbon. The preferred embodiment comprises a plurality of semiconductor films sandwiched together in layers, every three layers forming a PIN junction. All films are made of amorphous, hydrogenated carbon and vary only by dopant levels within each PIN junction. There are variations in bandgap from one PIN junction to the next in order that the photovoltaic effect in each PIN junction will be caused by a different portion of the spectrum of light.

Abstract translation: 一种包括多个膜层的光伏电池，所述层中的至少一个是非晶形氢化碳的半导体膜。 优选实施例包括多层半导体薄膜，每层三层形成PIN结。 所有薄膜都是由无定形碳氢化合物制成，并且仅在每个PIN结内的掺杂剂水平变化。 从一个PIN结到下一个PIN结的带隙有变化，以便每个PIN结中的光电效应将由光谱的不同部分引起。

公开(公告)号：US07163891B2

公开(公告)日：2007-01-16

申请号：US11003592

申请日：2004-12-03

Applicant: Michael Maldei ,  Brian Cousineau ,  Guenter Gerstmeier ,  Jon S. Berry, II ,  Steven M. Baker ,  Jinhwan Lee

Inventor： Michael Maldei ,  Brian Cousineau ,  Guenter Gerstmeier ,  Jon S. Berry, II ,  Steven M. Baker ,  Jinhwan Lee

IPC: H01L21/768

CPC classification number: H01L27/10894 ,  H01L27/10873

Abstract: A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

Abstract translation: 公开了一种在硅与栅极导体之间​​的距离小于0.14μm的动态随机存取存储器（DRAM）结构。 此外，公开了一种用于形成结构的方法，其包括同时形成DRAM阵列触点和与硅的触点。

公开(公告)号：US20050130352A1

公开(公告)日：2005-06-16

申请号：US11003592

申请日：2004-12-03

Applicant: Michael Maldei ,  Brian Cousineau ,  Guenter Gerstmeier ,  Jon Berry ,  Steven Baker ,  Jinhwan Lee

Inventor： Michael Maldei ,  Brian Cousineau ,  Guenter Gerstmeier ,  Jon Berry ,  Steven Baker ,  Jinhwan Lee

IPC: H01L21/336 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/10 ,  H01L29/40 ,  H01L29/739 ,  H01L29/76 ,  H01L29/78

CPC classification number: H01L27/10894 ,  H01L27/10873

Abstract: A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

Abstract translation: 公开了一种在硅与栅极导体之间​​的距离小于0.14μm的动态随机存取存储器（DRAM）结构。 此外，公开了一种用于形成结构的方法，其包括同时形成DRAM阵列触点和与硅的触点。

公开(公告)号：US06847092B2

公开(公告)日：2005-01-25

申请号：US10383191

申请日：2003-03-06

Applicant: Michael Maldei ,  Malati Hegde ,  Guenter Gerstmeier ,  Jinwhan Lee ,  Steven M. Baker ,  Jon S. Berry, II ,  Brian Cousineau ,  Wenchao Zheng

Inventor： Michael Maldei ,  Malati Hegde ,  Guenter Gerstmeier ,  Jinwhan Lee ,  Steven M. Baker ,  Jon S. Berry, II ,  Brian Cousineau ,  Wenchao Zheng

IPC: H01L21/02 ,  H01L27/08 ,  H01L29/94 ,  H01L29/72

CPC classification number: H01L28/40 ,  H01L27/0805 ,  H01L29/94

Abstract: A capacitor for a semiconductor device and a method of manufacturing a capacitor for a semiconductor device is disclosed that uses radial current flow. The capacitor includes a semiconductor substrate that includes a plurality of insulation islands. An insulation layer is formed over the semiconductor substrate. Gate electrodes are formed on top of the insulation layer. An array of CD contact pads including a plurality of CD contacts are connected to the semiconductor substrate in a first predetermined number of locations. An array of CG contact pads including at least one CG contact connected to the gate electrodes such that each CG contact is connected to a respective gate electrode above a respective insulation island in a second predetermined number of locations.

Abstract translation: 公开了一种用于半导体器件的电容器和制造用于半导体器件的电容器的方法，其使用径向电流流动。 电容器包括包括多个绝缘岛的半导体衬底。 在半导体衬底上形成绝缘层。 栅电极形成在绝缘层的顶部。 包括多个CD触点的CD接触焊盘的阵列在第一预定数量的位置连接到半导体衬底。 一种CG接触焊盘的阵列，包括连接到栅电极的至少一个CG触点，使得每个CG触点在第二预定数量的位置中连接到相应绝缘岛上方的相应栅电极。