公开(公告)号：US20070118242A1

公开(公告)日：2007-05-24

申请号：US11503433

申请日：2006-08-10

Applicant: Brian Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph Davis ,  Purnendu Mozumder ,  Sherry Lee ,  Larg Weiland ,  Dennis Ciplickas ,  David Stashower

Inventor： Brian Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph Davis ,  Purnendu Mozumder ,  Sherry Lee ,  Larg Weiland ,  Dennis Ciplickas ,  David Stashower

IPC: G06F19/00

CPC classification number: G06F17/5081 ,  G05B15/02 ,  H01L22/20 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

Abstract translation: 用于预测集成电路的产量的系统和方法包括至少一种表征车辆，其包括至少一个特征，其代表要并入到最终集成电路产品中的至少一种类型的特征。 表征车辆经受构成制造周期的工艺操作中的至少一个，以用于制造集成电路产品以产生屈服模型。 产量模型体现了由表征车辆定义的布局，并且优选地包括便于在运行速度下收集电测试数据和测试原型部分的特征。 提取引擎从提出的产品布局中提取预定的布局属性。 在产量模型上运行，提取引擎作为布局属性的函数产生产量预测，并在制造过程中按层或步骤细分。 然后使用这些产量预测来确定制造过程中哪些领域需要最大的改进。

公开(公告)号：US20050158888A1

公开(公告)日：2005-07-21

申请号：US11078630

申请日：2005-03-10

Applicant: Brian Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph Davis ,  Purnendu Mozumder ,  Sherry Lee ,  Larg Weiland ,  Dennis Ciplickas ,  David Stashower

Inventor： Brian Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph Davis ,  Purnendu Mozumder ,  Sherry Lee ,  Larg Weiland ,  Dennis Ciplickas ,  David Stashower

IPC: H01L21/00 ,  G01R31/26 ,  G05B15/02 ,  H01L21/02 ,  H01L21/66 ,  H01L23/544

CPC classification number: G06F17/5081 ,  G05B15/02 ,  H01L22/20 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

Abstract translation: 用于预测集成电路的产量的系统和方法包括至少一种表征车辆，其包括至少一个特征，其代表要并入到最终集成电路产品中的至少一种类型的特征。 表征车辆经受构成制造周期的工艺操作中的至少一个，以用于制造集成电路产品以产生屈服模型。 产量模型体现了由表征车辆定义的布局，并且优选地包括便于在运行速度下收集电测试数据和测试原型部分的特征。 提取引擎从提出的产品布局中提取预定的布局属性。 在产量模型上运行，提取引擎作为布局属性的函数产生产量预测，并在制造过程中按层或步骤细分。 然后使用这些产量预测来确定制造过程中哪些领域需要最大的改进。

公开(公告)号：US20060277506A1

公开(公告)日：2006-12-07

申请号：US11503323

申请日：2006-08-10

Applicant: Brian Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph Davis ,  Purnendu Mozumder ,  Sherry Lee ,  Larg Weiland ,  Dennis Ciplickas ,  David Stashower

Inventor： Brian Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph Davis ,  Purnendu Mozumder ,  Sherry Lee ,  Larg Weiland ,  Dennis Ciplickas ,  David Stashower

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G05B15/02 ,  H01L22/20 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

公开(公告)号：US5548548A

公开(公告)日：1996-08-20

申请号：US358647

申请日：1994-12-19

Applicant: Amitava Chatterjee ,  Jiann Liu ,  Purnendu Mozumder ,  Mark S. Rodder ,  Ih-Chin Chen

Inventor： Amitava Chatterjee ,  Jiann Liu ,  Purnendu Mozumder ,  Mark S. Rodder ,  Ih-Chin Chen

IPC: H01L29/78 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/10 ,  H01L29/423 ,  G11C11/401

CPC classification number: H01L27/10873 ,  G11C11/404 ,  H01L29/1087 ,  H01L29/42364 ,  H01L29/42376

Abstract: A design to attain a pass transistor for a 256 Mbit DRAM part. The transistor having a gate length of about 0.3 .mu.m, a t.sub.ox of about 85 .ANG., which is much thicker than the .about.65 .ANG. t.sub.ox for 0.25 .mu.m logic technology, a V.sub.WL of 3.75 V, a V.sub.sub of -1 V, arsenic LDD and a boron concentration in the channel region of about 2.7.times.10.sup.17 /cm.sup.3 are the desired technological choices for 256 Mbit DRAM devices.

Abstract translation: 实现256 Mbit DRAM器件的传输晶体管的设计。 栅极长度约为0.3μm的晶体管，约为85安培的毒素，其比0.25微米逻辑技术的DIFFERENCE 65 ANGSTROM毒is厚，V VL为3.75伏，Vsub为-1伏，砷 LDD和沟道区域中的硼浓度约为2.7x1017 / cm3，是256 Mbit DRAM器件的理想选择。