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1.发明授权Memory device and system with cyclic, ECC-corrected bootloading operation during voltage bring up 失效存储器件和系统在电压提升期间具有循环，ECC校正的引导加载操作公开(公告)号：US07975178B2
公开(公告)日：2011-07-05
申请号：US12208565
申请日：2008-09-11
Applicant: Chang-Rae Kim , Pyung-Moon Zhang
Inventor： Chang-Rae Kim , Pyung-Moon Zhang
CPC classification number: G06F11/1417 , G06F11/1004 , G06F11/2284
Abstract: Provided are a semiconductor memory device, memory system and method of executing a bootloading operation. The method includes cyclically executing a bootloading operation cycle that includes loading the boot information from the memory to the controller, and performing an ECC operation on the boot information. The ECC operation provides a fail condition indication or a pass condition indication and if the fail condition indication is provided, the next bootloading operation cycle is executed.
Abstract translation: 提供了一种半导体存储器件，存储器系统和执行引导加载操作的方法。 该方法包括循环地执行引导操作循环，其包括将来自存储器的引导信息加载到控制器，以及对引导信息执行ECC操作。 ECC操作提供故障状态指示或通过条件指示，并且如果提供了故障状态指示，则执行下一个引导加载操作循环。
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公开(公告)号：US07002869B2
公开(公告)日：2006-02-21
申请号：US10794532
申请日：2004-03-05
Applicant: Pyung-Moon Zhang , Seung-Keun Lee
Inventor： Pyung-Moon Zhang , Seung-Keun Lee
IPC: G11C7/00
Abstract: A voltage regulator circuit and a semiconductor memory device using the same are provided. The voltage regulator circuit regulates an input voltage to provide an output voltage. The voltage regulator circuit comprises a voltage divider to divide the output voltage, a comparator to determine whether the divided voltage is less than a reference voltage, a driver connected between the input voltage and the output voltage, and operating operate responsive to the comparator, and a controller to control the voltage divider to gradually vary the output voltage. The voltage divider includes a resistance that operates responsive to the controller and whose value varies in a binary weighted form.
Abstract translation: 提供了一种电压调节器电路和使用其的半导体存储器件。 电压调节器电路调节输入电压以提供输出电压。 电压调节器电路包括用于分压输出电压的分压器，用于确定分压是否小于参考电压的比较器，连接在输入电压和输出电压之间的驱动器，以及响应于比较器的操作操作，以及 一个控制器来控制分压器逐渐改变输出电压。 分压器包括响应于控制器操作的电阻，其值以二进制加权形式变化。
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公开(公告)号：US20100214866A1
公开(公告)日：2010-08-26
申请号：US12708188
申请日：2010-02-18
Applicant: Pyung-Moon Zhang
Inventor： Pyung-Moon Zhang
IPC: G11C8/18
Abstract: A semiconductor memory device includes an internal clock generator configured to generate an internal clock signal having a first clock period in response to a chip enable signal and change the first clock period of the internal clock signal in response to a clock control signal, and a controller configured to receive external commands including the chip enable signal and generate the clock control signal corresponding to a first external command other than the chip enable signal. Here, the semiconductor memory device performs a data input/output operation in response to the internal clock signal with the changed clock period.
Abstract translation: 半导体存储器件包括：内部时钟发生器，被配置为响应于芯片使能信号产生具有第一时钟周期的内部时钟信号，并且响应于时钟控制信号改变内部时钟信号的第一时钟周期;以及控制器 被配置为接收包括所述芯片使能信号的外部命令，并且生成与除了所述芯片使能信号之外的第一外部命令相对应的时钟控制信号。 这里，半导体存储器件响应具有改变的时钟周期的内部时钟信号执行数据输入/输出操作。
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4.发明申请Oscillation circuits including latches for integrated circuit devices and related methods 有权振荡电路包括用于集成电路器件的锁存器和相关方法公开(公告)号：US20060061422A1
公开(公告)日：2006-03-23
申请号：US11021587
申请日：2004-12-22
Applicant: Hyun-Duk Cho , Pyung-Moon Zhang
Inventor： Hyun-Duk Cho , Pyung-Moon Zhang
IPC: H03L7/085
Abstract: An oscillator circuit may include a latch circuit, a feed-back circuit, and an input circuit. The latch circuit may be configured to generate an oscillating output signal responsive to first and second input signals, and the feed-back circuit may be configured to generate first and second complementary feed-back signals responsive to the oscillating output signal from the latch circuit. The input circuit may be configured to generate the first and second input signals responsive to the first and second complementary feed-back signals. Related methods are also discussed.
Abstract translation: 振荡器电路可以包括锁存电路，反馈电路和输入电路。 锁存电路可以被配置为响应于第一和第二输入信号产生振荡输出信号，并且反馈电路可以被配置为响应于来自锁存电路的振荡输出信号而产生第一和第二互补反馈信号。 输入电路可以被配置为响应于第一和第二互补反馈信号产生第一和第二输入信号。 还讨论了相关方法。
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公开(公告)号：US20050007187A1
公开(公告)日：2005-01-13
申请号：US10888667
申请日：2004-07-08
Applicant: Pyung-Moon Zhang , Seung-Keun Lee
Inventor： Pyung-Moon Zhang , Seung-Keun Lee
CPC classification number: H02M3/073
Abstract: Disclosed is a charge pump circuit that operates responsive to a test or general operation mode. The charge pump circuit includes at least one charge pump part. A voltage level sensing block generates a level sensing signal by sensing an output voltage. An oscillator generates complementary pulse signals responsive to the level sensing signal. And a selecting circuit block generates a selected voltage that is one of a high voltage and a supply voltage to the at least one charge pump part, the high voltage having a level higher than the supply voltage.
Abstract translation: 公开了一种响应于测试或一般操作模式操作的电荷泵电路。 电荷泵电路包括至少一个电荷泵部分。 电压电平检测块通过检测输出电压来产生电平检测信号。 振荡器响应于电平感测信号产生互补的脉冲信号。 并且选择电路块产生对至少一个电荷泵部分的高电压和电源电压之一的选定电压，高电压具有高于电源电压的电平。
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Patent Agency Ranking
公开(公告)号：US08279699B2
公开(公告)日：2012-10-02
申请号：US12708188
申请日：2010-02-18
Applicant: Pyung-Moon Zhang
Inventor： Pyung-Moon Zhang
IPC: G11C8/00
Abstract: A semiconductor memory device includes an internal clock generator configured to generate an internal clock signal having a first clock period in response to a chip enable signal and change the first clock period of the internal clock signal in response to a clock control signal, and a controller configured to receive external commands including the chip enable signal and generate the clock control signal corresponding to a first external command other than the chip enable signal. Here, the semiconductor memory device performs a data input/output operation in response to the internal clock signal with the changed clock period.
Abstract translation: 半导体存储器件包括：内部时钟发生器，被配置为响应于芯片使能信号产生具有第一时钟周期的内部时钟信号，并且响应于时钟控制信号改变内部时钟信号的第一时钟周期;以及控制器 被配置为接收包括所述芯片使能信号的外部命令，并且生成与除了所述芯片使能信号之外的第一外部命令相对应的时钟控制信号。 这里，半导体存储器件响应具有改变的时钟周期的内部时钟信号执行数据输入/输出操作。
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公开(公告)号：US20090077423A1
公开(公告)日：2009-03-19
申请号：US12208565
申请日：2008-09-11
Applicant: Chang-Rae KIM , Pyung-Moon ZHANG
Inventor： Chang-Rae KIM , Pyung-Moon ZHANG
CPC classification number: G06F11/1417 , G06F11/1004 , G06F11/2284
Abstract: Provided are a semiconductor memory device, memory system and method of executing a bootloading operation. The method includes cyclically executing a bootloading operation cycle that includes loading the boot information from the memory to the controller, and performing an ECC operation on the boot information. The ECC operation provides a fail condition indication or a pass condition indication and if the fail condition indication is provided, the next bootloading operation cycle is executed.
Abstract translation: 提供了一种半导体存储器件，存储器系统和执行引导加载操作的方法。 该方法包括循环地执行引导操作循环，其包括将来自存储器的引导信息加载到控制器，以及对引导信息执行ECC操作。 ECC操作提供故障状态指示或通过条件指示，并且如果提供了故障状态指示，则执行下一个引导加载操作循环。
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公开(公告)号：US07443728B2
公开(公告)日：2008-10-28
申请号：US11242013
申请日：2005-10-04
Applicant: Jin-Wook Lee , Pyung-Moon Zhang
Inventor： Jin-Wook Lee , Pyung-Moon Zhang
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/24
Abstract: Disclosed is a NAND flash memory device comprising a memory cell array connected to a page buffer via a plurality of bitlines. The page buffer stores input data to be programmed in the memory cell array. The memory cell array is programmed by establishing bitline voltages for the plurality of bitlines according to the input data and then applying a wordline voltage to the memory cell array. The bitline voltages are established by first precharging the bitlines to a power supply voltage and then selectively discharging the bitlines according to the input data. The bitlines are discharged sequentially, i.e., some of the bitlines are discharged before others.
Abstract translation: 公开了一种NAND闪速存储器件，其包括通过多个位线连接到页缓冲器的存储单元阵列。 页面缓冲器将要编程的输入数据存储在存储单元阵列中。 通过根据输入数据建立多个位线的位线电压，然后将字线电压施加到存储单元阵列来编程存储单元阵列。 位线电压通过首先将位线预充电到电源电压，然后根据输入数据选择性地排放位线来建立。 位线依次放电，即某些位线在其他位线之前被放电。
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公开(公告)号：US07427888B2
公开(公告)日：2008-09-23
申请号：US10888667
申请日：2004-07-08
Applicant: Pyung-Moon Zhang , Seung-Keun Lee
Inventor： Pyung-Moon Zhang , Seung-Keun Lee
IPC: G05F1/10
CPC classification number: H02M3/073
Abstract: Disclosed is a charge pump circuit that operates responsive to a test or general operation mode. The charge pump circuit includes at least one charge pump part. A voltage level sensing block generates a level sensing signal by sensing an output voltage. An oscillator generates complementary pulse signals responsive to the level sensing signal. And a selecting circuit block generates a selected voltage that is one of a high voltage and a supply voltage to the at least one charge pump part, the high voltage having a level higher than the supply voltage.
Abstract translation: 公开了一种响应于测试或一般操作模式操作的电荷泵电路。 电荷泵电路包括至少一个电荷泵部分。 电压电平检测块通过检测输出电压来产生电平检测信号。 振荡器响应于电平感测信号产生互补的脉冲信号。 并且选择电路块产生对至少一个电荷泵部分的高电压和电源电压之一的选定电压，高电压具有高于电源电压的电平。
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10.发明授权Oscillation circuits including latches for integrated circuit devices and related methods 有权振荡电路包括用于集成电路器件的锁存器和相关方法公开(公告)号：US07167060B2
公开(公告)日：2007-01-23
申请号：US11021587
申请日：2004-12-22
Applicant: Hyun-Duk Cho , Pyung-Moon Zhang
Inventor： Hyun-Duk Cho , Pyung-Moon Zhang
IPC: H03K3/27
Abstract: An oscillator circuit may include a latch circuit, a feed-back circuit, and an input circuit. The latch circuit may be configured to generate an oscillating output signal responsive to first and second input signals, and the feed-back circuit may be configured to generate first and second complementary feed-back signals responsive to the oscillating output signal from the latch circuit. The input circuit may be configured to generate the first and second input signals responsive to the first and second complementary feed-back signals. Related methods are also discussed.
Abstract translation: 振荡器电路可以包括锁存电路，反馈电路和输入电路。 锁存电路可以被配置为响应于第一和第二输入信号产生振荡输出信号，并且反馈电路可以被配置为响应于来自锁存电路的振荡输出信号而产生第一和第二互补反馈信号。 输入电路可以被配置为响应于第一和第二互补反馈信号产生第一和第二输入信号。 还讨论了相关方法。
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