Selectively combining signals to produce desired output signal

    公开(公告)号:US06812761B2

    公开(公告)日:2004-11-02

    申请号:US10670697

    申请日:2003-09-24

    CPC classification number: H03K5/1534 H03K5/06 H03K5/13

    Abstract: The present invention provides a mechanism for combining programming signals to provide an output signal, the properties of which depend only on selected properties of the programming signals. An embodiment of the invention includes first and second edge-to-pulse converters. The first edge-to-pulse converter generates an intermediate signal having a width determined by received initiation and termination signals. The second edge-to-pulse converter generates an output signal, responsive to the intermediate signal and the termination signal. The output signal has a width determined by a first edge of the initiation signal and a first edge of the termination signal.

    Interconnecting of digital devices
    4.
    发明授权
    Interconnecting of digital devices 失效
    数字设备互连

    公开(公告)号:US07199681B2

    公开(公告)日:2007-04-03

    申请号:US10126754

    申请日:2002-04-19

    CPC classification number: G06F13/4086 H03H7/38 H03H7/48

    Abstract: In some embodiments, a first conducting line, having a characteristic impedance, connects to a digital device while a second conducting line, also having a characteristic impedance, connects to another digital device. An impedance pathway connects the two conducting lines and has an impedance of at least one-third of the first conducting line's characteristic impedance and of at least one-third of the second conducting line's characteristic impedances. Other embodiments are claimed.

    Abstract translation: 在一些实施例中,具有特征阻抗的第一导线连接到数字装置,而具有特征阻抗的第二导线连接到另一数字装置。 阻抗路径连接两条导线,并且具有至少第一导线特性阻抗的三分之一的阻抗和至少第三导线的特征阻抗的三分之一的阻抗。 要求保护其他实施例。

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