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    TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS
    1.
    发明申请
    TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS 审中-公开
    形成功能性细胞压制阵列的技术

    公开(公告)号：US20170018543A1

    公开(公告)日：2017-01-19

    申请号：US15124817

    申请日：2014-06-25

    申请人： Rany T. ELSAYED ,  Niti GOEL ,  Silvio E. BOU-GHAZALE ,  Randy J. AKSAMIT

    发明人： Rany T. ELSAYED ,  Niti GOEL ,  Silvio E. BOU-GHAZALE ,  Randy J. AKSAMIT

    IPC分类号： H01L27/02 ,  H01L21/027 ,  H01L27/118 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/16

    CPC分类号： H01L27/0207 ,  G06F17/5068 ,  H01L21/0274 ,  H01L21/0277 ,  H01L21/823475 ,  H01L27/11 ,  H01L27/11807 ,  H01L29/16 ,  H01L2027/11853 ,  H01L2027/11866 ,  H01L2027/11875 ,  H03K19/00

    摘要： Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.

    摘要翻译： 公开了用于使用下一代光刻（NGL）工艺（例如电子束直写（EBDW）和极紫外光刻（EUVL））形成功能电池的压实阵列的技术，以形成阵列中的电池的边界。 紧凑的单元阵列可以用于配置有逻辑单元，配置有位单元的静态随机存取存储器（SRAM）结构或具有基于单元的结构的其他存储器或逻辑器件的现场可编程门阵列（FPGA）结构。 与常规的193nm光刻相比，这些技术可以用于获得10至50％的面积减少，例如对于功能单元阵列，因为NGL工艺允许更高的精度和更小的细胞边界切割 。 此外，使用NGL工艺来形成单元的边界也可以减少光刻引起的变化，否则将以传统的193nm光刻法存在。

    Low leakage state retention circuit
    2.
    发明申请
    Low leakage state retention circuit 失效
    低泄漏状态保持电路

    公开(公告)号：US20080238510A1

    公开(公告)日：2008-10-02

    申请号：US11731226

    申请日：2007-03-30

    申请人： Randy J. Aksamit

    发明人： Randy J. Aksamit

    IPC分类号： H03K3/02

    CPC分类号： H03K3/0375

    摘要： In general, in one aspect, the disclosure describes an apparatus comprising a low leakage latch to store a state of a circuit during inactive periods. The state is transferred to the low leakage latch upon receipt of an inactive pulse. A buffer is used to receive the state from an output of the low leakage latch and to isolate the state. State restore circuitry is used to restore the state to the circuit when the circuit returns to an active mode. The state restore circuitry is used to receive the isolated state and to restore the state upon receipt of an active pulse.

    摘要翻译： 通常，在一个方面，本公开描述了一种包括低泄漏锁存器以在非活动时段期间存储电路的状态的装置。 收到无效脉冲后，状态转移到低泄漏锁存器。 缓冲器用于从低泄漏锁存器的输出接收状态并隔离状态。 当电路恢复到活动模式时，状态恢复电路用于恢复电路的状态。 状态恢复电路用于接收隔离状态，并在接收到有效脉冲时恢复状态。

    Two-latch clocked-LSSD flip-flop
    3.
    发明授权
    Two-latch clocked-LSSD flip-flop 有权
    双锁定时钟LSSD触发器

    公开(公告)号：US07262648B2

    公开(公告)日：2007-08-28

    申请号：US10909382

    申请日：2004-08-03

    申请人： Randy J. Aksamit

    发明人： Randy J. Aksamit

    IPC分类号： H03K3/289 ,  H03K3/356

    CPC分类号： H03K3/0375 ,  G01R31/318541 ,  G01R31/318594

    摘要： A clocked level-sensitive scan design may have flip-flops designed to have data, scan-in, and output ports and to utilize two clock signals. Such a clocked level-sensitive scan flip-flop may be built utilizing two latches.

    摘要翻译： 时钟电平敏感扫描设计可能具有设计为具有数据，扫描和输出端口并使用两个时钟信号的触发器。 可以利用两个锁存器构建这样的时钟电平敏感扫描触发器。

    Gate array architecture
    5.
    发明授权
    Gate array architecture 失效
    门阵列架构

    公开(公告)号：US06462583B2

    公开(公告)日：2002-10-08

    申请号：US09912639

    申请日：2001-07-24

    申请人： Randy J. Aksamit

    发明人： Randy J. Aksamit

    IPC分类号： H03K1900

    CPC分类号： H01L27/0207 ,  H01L27/11807

    摘要： Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes at least one base site, the at least one base site being three tracks wide and including four N-type transistors and four P-type transistors. Briefly, in accordance with another embodiment of the invention, a method of fabricating an integrated circuit chip includes: processing a semiconductor substrate to form a gate array architecture of transistors in the substrate. The gate array architecture includes at least one base site being three tracks wide and including four N-type transistors and four P-type transistors. Briefly, in accordance with still another embodiment of the invention, an article includes: a storage medium, the storage medium having instructions stored thereon, the instructions, when executed, resulting in the capability to design the layout of an integrated circuit chip for fabrication, the integrated circuit chip including a gate array architecture, the gate array architecture including at least one base site being three tracks wide and including four N-type transistors and four P-type transistors.

    摘要翻译： 简而言之，根据本发明的一个实施例，集成电路包括：门阵列结构。 门阵列结构包括至少一个基站，所述至少一个基站位于三个宽度的宽度，并且包括四个N型晶体管和四个P型晶体管。 简而言之，根据本发明的另一个实施例，制造集成电路芯片的方法包括：处理半导体衬底以在衬底中形成晶体管的栅极阵列结构。 门阵列结构包括至少一个基准位置，三个宽度的轨道，包括四个N型晶体管和四个P型晶体管。 简而言之，根据本发明的另一实施例，一种物品包括：存储介质，其上存储有指令的存储介质，所述指令在执行时导致设计用于制造的集成电路芯片的布局的能力， 所述集成电路芯片包括门阵列结构，所述门阵列结构包括至少一个基本位置，其具有三个磁道宽，并且包括四个N型晶体管和四个P型晶体管。

    Low leakage state retention circuit
    7.
    发明授权
    Low leakage state retention circuit 失效
    低泄漏状态保持电路

    公开(公告)号：US07626434B2

    公开(公告)日：2009-12-01

    申请号：US11731226

    申请日：2007-03-30

    申请人： Randy J. Aksamit

    发明人： Randy J. Aksamit

    IPC分类号： H03K3/289 ,  H03K3/356

    CPC分类号： H03K3/0375

    摘要： In general, in one aspect, the disclosure describes an apparatus comprising a low leakage latch to store a state of a circuit during inactive periods. The state is transferred to the low leakage latch upon receipt of an inactive pulse. A buffer is used to receive the state from an output of the low leakage latch and to isolate the state. State restore circuitry is used to restore the state to the circuit when the circuit returns to an active mode. The state restore circuitry is used to receive the isolated state and to restore the state upon receipt of an active pulse.

    摘要翻译： 通常，在一个方面，本公开描述了一种包括低泄漏锁存器以在非活动时段期间存储电路的状态的装置。 收到无效脉冲后，状态转移到低泄漏锁存器。 缓冲器用于从低泄漏锁存器的输出接收状态并隔离状态。 当电路恢复到活动模式时，状态恢复电路用于恢复电路的状态。 状态恢复电路用于接收隔离状态，并在接收到有效脉冲时恢复状态。

    Two-latch clocked-LSSD flip-flop
    8.
    发明授权
    Two-latch clocked-LSSD flip-flop 有权
    双锁定时钟LSSD触发器

    公开(公告)号：US07492201B2

    公开(公告)日：2009-02-17

    申请号：US11845553

    申请日：2007-08-27

    申请人： Randy J. Aksamit

    发明人： Randy J. Aksamit

    IPC分类号： H03K3/289

    CPC分类号： H03K3/0375 ,  G01R31/318541 ,  G01R31/318594

    摘要： A clocked level-sensitive scan design may have flip-flops designed to have data, scan-in, and output ports and to utilize two clock signals. Such a clocked level-sensitive scan flip-flop may be built utilizing two latches.

    摘要翻译： 时钟电平敏感扫描设计可能具有设计为具有数据，扫描和输出端口并使用两个时钟信号的触发器。 可以利用两个锁存器构建这样的时钟电平敏感扫描触发器。

    System and method for data retention with reduced leakage current
    9.
    发明授权
    System and method for data retention with reduced leakage current 失效
    具有减少泄漏电流的数据保留系统和方法

    公开(公告)号：US07170327B2

    公开(公告)日：2007-01-30

    申请号：US10608055

    申请日：2003-06-27

    申请人： Randy J. Aksamit

    发明人： Randy J. Aksamit

    IPC分类号： H03K3/289

    CPC分类号： H01L27/0207

    摘要： In embodiments, a data-retention circuitry comprises data-retention inverters in a feedback loop, an isolation subcircuit to isolate the inverters from a pass-gate subcircuit in response to a sleep signal, and a supply-switching subcircuit to provide current to the data-retention inverters from a supplemental voltage supply through a well tap during a standby mode. The supply-switching subcircuit switches from a regular voltage supply to the supplemental voltage supply in response to the sleep signal.

    摘要翻译： 在实施例中，数据保持电路包括反馈回路中的数据保持反相器，响应于睡眠信号将反相器与通过门子电路隔离的隔离子电路，以及向数据提供电流的电源切换子电路 在待机模式期间，通过井口从补充电压供应器中保留逆变器。 电源切换分支电路响应于睡眠信号从常规电压电源切换到补充电源。

    Gate array architecture
    10.
    发明授权
    Gate array architecture 失效
    门阵列架构

    公开(公告)号：US06480032B1

    公开(公告)日：2002-11-12

    申请号：US09262459

    申请日：1999-03-04

    申请人： Randy J. Aksamit

    发明人： Randy J. Aksamit

    IPC分类号： H03K1900

    CPC分类号： H01L27/0207 ,  H01L27/11807

    摘要： Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes at least one base site, the at least one base site being three tracks wide and including four N-type transistors and four P-type transistors. Briefly, in accordance with another embodiment of the invention, a method of fabricating an integrated circuit chip includes: processing a semiconductor substrate to form a gate array architecture of transistors in the substrate. The gate array architecture includes at least one base site being three tracks wide and including four N-type transistors and four P-type transistors. Briefly, in accordance with still another embodiment of the invention, an article includes: a storage medium, the storage medium having instructions stored thereon, the instructions, when executed, resulting in the capability to design the layout of an integrated circuit chip for fabrication, the integrated circuit chip including a gate array architecture, the gate array architecture including at least one base site being three tracks wide and including four N-type transistors and four P-type transistors.

    摘要翻译： 简而言之，根据本发明的一个实施例，集成电路包括：门阵列结构。 门阵列架构包括至少一个基站，所述至少一个基站位于三个宽度的宽度，并且包括四个N型晶体管和四个P型晶体管。简而言之，根据本发明的另一实施例，一种制造方法 集成电路芯片包括：处理半导体衬底以在衬底中形成晶体管的栅阵列架构。 门阵列结构包括至少一个基准位置，三个轨道宽，包括四个N型晶体管和四个P型晶体管。简而言之，根据本发明的另一个实施例，一种物品包括：存储介质，存储器 具有存储在其上的指令的介质，所述指令在被执行时导致设计用于制造的集成电路芯片的布局的能力，所述集成电路芯片包括门阵列架构，所述门阵列架构包括至少一个基站 轨道宽，包括四个N型晶体管和四个P型晶体管。