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    Bipolar transistor structure with a shallow isolation extension region providing reduced parasitic capacitance
    5.
    发明授权
    Bipolar transistor structure with a shallow isolation extension region providing reduced parasitic capacitance 失效
    具有浅隔离延伸区域的双极晶体管结构，提供降低的寄生电容

    公开(公告)号：US06864560B2

    公开(公告)日：2005-03-08

    申请号：US10249299

    申请日：2003-03-28

    申请人： Marwan H. Khater ,  Jae-Sung Rieh ,  Andreas Daniel Stricker ,  Gregory Gower Freeman ,  Kathryn Turner Schonenberg

    发明人： Marwan H. Khater ,  Jae-Sung Rieh ,  Andreas Daniel Stricker ,  Gregory Gower Freeman ,  Kathryn Turner Schonenberg

    IPC分类号： H01L29/70 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L27/082 ,  H01L27/102 ,  H01L31/11

    CPC分类号： H01L29/66287 ,  H01L29/0649 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

    摘要： A bipolar vertical transistor is formed in a silicon semiconductor substrate which has an upper surface with STI regions formed therein composed of a dielectric material formed in the substrate having inner ends and top surfaces. A doped collector region is formed in the substrate between a pair of the STI regions. A counterdoped intrinsic base region is formed on the upper surface of the substrate between the pair of the STI regions with a margin between the intrinsic base region and the pair of STI regions, the intrinsic base region having edges. A doped emitter region is formed above the intrinsic base region spaced away from the edges. A shallow isolation extension region composed of a dielectric material is next to the edges of the intrinsic base region formed in the margin between the STI regions and the intrinsic base region. An extrinsic base region covers the shallow isolation extension region and extends partially over the intrinsic base region in mechanical and electrical contact therewith, whereby the shallow isolation extension region reduces the base-to-collector parasitic capacitance of the bipolar transistor.

    摘要翻译： 双极性垂直晶体管形成在硅半导体衬底中，该硅半导体衬底具有形成有STI区域的上表面，该区域由形成在具有内端和顶表面的衬底中的电介质材料构成。 掺杂的集电极区域形成在一对STI区域之间的衬底中。 在本体基极区域和一对STI区域之间的边缘部分之间形成反向掺杂的本征基极区域，该反向掺杂的本征基极区域位于一对STI区域之间的衬底的上表面上，本征基极区域具有边缘。 掺杂的发射极区域形成在与边缘间隔开的本征基极区域上方。 由介电材料构成的浅隔离延伸区域紧邻在STI区域和本征基极区域之间的边缘中形成的本征基极区域的边缘。 外部基极区域覆盖浅隔离延伸区域并且在与本体基极区域机械和电接触的同时部分延伸，由此浅隔离延伸区域减小双极晶体管的基极到集电极寄生电容。

    Self-aligned mask formed utilizing differential oxidation rates of materials
    6.
    发明授权
    Self-aligned mask formed utilizing differential oxidation rates of materials 有权
    使用材料的不同氧化速率形成的自对准掩模

    公开(公告)号：US07288827B2

    公开(公告)日：2007-10-30

    申请号：US10969718

    申请日：2004-10-20

    申请人： Huajie Chen ,  Kathryn T. Schonenberg ,  Gregory G. Freeman ,  Andreas D. Stricker ,  Jae-Sung Rieh

    发明人： Huajie Chen ,  Kathryn T. Schonenberg ,  Gregory G. Freeman ,  Andreas D. Stricker ,  Jae-Sung Rieh

    IPC分类号： H01L27/082 ,  H01L27/102

    CPC分类号： H01L29/66242 ,  H01L21/32105 ,  Y10S438/911

    摘要： A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation. This self-aligned oxide mask blocks B diffusion from the raised extrinsic base to the corner of collector.

    摘要翻译： 使用不同材料的不同氧化速率形成自对准氧化物掩模。 自对准氧化物掩模形成在CVD生长的基底NPN基层上，其牺牲了场上的活性区域上的单晶Si（或Si / SiGe）和多晶Si（或Si / SiGe）。 通过利用多晶硅（或Si / SiGe）比单晶Si（或Si / SiGe）更快地氧化的事实来制造自对准掩模。 通过使用热氧化工艺在多晶硅（或Si / siGe）和单晶Si（或Si / siGe）上形成氧化膜，以在多晶硅（或Si / SiGe）上形成厚的氧化层，以及 在单晶Si（或Si / siGe）上方的薄氧化层，随后进行受控氧化物蚀刻以除去单晶Si（或Si / siGe）上的薄氧化层，同时将自对准氧化物掩模层留在 多晶硅（或Si / siGe）。 然后在自对准掩模形成之后形成隆起的外在基体。 该自对准氧化物掩模阻挡从扩展的外在碱基到收集器角的扩散。

    Self-aligned mask formed utilizing differential oxidation rates of materials
    7.
    发明授权
    Self-aligned mask formed utilizing differential oxidation rates of materials 失效
    使用材料的不同氧化速率形成的自对准掩模

    公开(公告)号：US06844225B2

    公开(公告)日：2005-01-18

    申请号：US10345469

    申请日：2003-01-15

    申请人： Huajie Chen ,  Kathryn T. Schonenberg ,  Gregory G. Freeman ,  Andreas D. Stricker ,  Jae-Sung Rieh

    发明人： Huajie Chen ,  Kathryn T. Schonenberg ,  Gregory G. Freeman ,  Andreas D. Stricker ,  Jae-Sung Rieh

    IPC分类号： H01L21/321 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L21/00

    CPC分类号： H01L29/66242 ,  H01L21/32105 ,  Y10S438/911

    摘要： A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation. This self-aligned oxide mask blocks B diffusion from the raised extrinsic base to the corner of collector.

    摘要翻译： 使用不同材料的不同氧化速率形成自对准氧化物掩模。 自对准氧化物掩模形成在CVD生长的基底NPN基层上，其牺牲了场上的活性区域上的单晶Si（或Si / SiGe）和多晶Si（或Si / SiGe）。 通过利用多晶硅（或Si / SiGe）比单晶Si（或Si / SiGe）更快地氧化的事实来制造自对准掩模。 通过使用热氧化工艺在多晶硅（或Si / siGe）和单晶Si（或Si / siGe）上形成氧化膜，以在多晶硅（或Si / SiGe）上形成厚的氧化层，以及 在单晶Si（或Si / siGe）上方的薄氧化层，随后进行受控氧化物蚀刻以除去单晶Si（或Si / siGe）上的薄氧化层，同时将自对准氧化物掩模层留在 多晶硅（或Si / siGe）。 然后在自对准掩模形成之后形成隆起的外在基体。 该自对准氧化物掩模阻挡从扩展的外在碱基到收集器角的扩散。

    Methods of base formation in a BiCMOS process
    9.
    发明申请
    Methods of base formation in a BiCMOS process 失效
    BiCMOS工艺中碱形成的方法

    公开(公告)号：US20060017066A1

    公开(公告)日：2006-01-26

    申请号：US11231385

    申请日：2005-09-21

    申请人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

    发明人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

    IPC分类号： H01L31/109

    CPC分类号： H01L29/66242 ,  H01L21/28518 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/456 ,  H01L29/7371

    摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

    摘要翻译： 提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。 在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。 本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。 凸起的外基极上面的硅化物以自对准的方式延伸到发射极。 发射极通过间隔物与硅化物分离。

    MOS VARACTOR AND FABRICATING METHOD OF THE SAME
    10.
    发明申请
    MOS VARACTOR AND FABRICATING METHOD OF THE SAME 有权
    MOS变压器及其制作方法

    公开(公告)号：US20100244113A1

    公开(公告)日：2010-09-30

    申请号：US12565197

    申请日：2009-09-23

    申请人： Jae-Sung Rieh ,  Yong Ho Oh ,  Sue Yeon Kim ,  Seung Yong Lee

    发明人： Jae-Sung Rieh ,  Yong Ho Oh ,  Sue Yeon Kim ,  Seung Yong Lee

    IPC分类号： H01L29/93 ,  H01L21/329

    CPC分类号： H01L29/93 ,  H01L29/66174

    摘要： The present invention provides a MOS varactor for use in circuits and elements of a millimeter-wave frequency band, which is capable of reducing series resistance and enhancing a Q-factor by using a plurality of island-like gates seated in a well region of a substrate and gate contacts directly over the gates, and a method of fabricating the MOS varactor. The MOS varactor include: island-like gate insulating layers which are arranged at equal intervals in the form of a (n×m) matrix (where, n and m are integers equal to or larger than one), and a gate electrode of a first height (t1) placed on the gate insulating layers in a well region of a substrate; a gate contact which contacts the gate electrode; a first metal wire of a second height (t2) (where, t1

    摘要翻译： 本发明提供一种用于毫米波频带的电路和元件的MOS可变电抗器，其能够通过使用位于一个或多个的区域中的多个岛状门来降低串联电阻并提高Q因子 衬底和栅极直接连接在栅极上，以及制造MOS变容二极管的方法。 MOS变容二极管包括：以（n×m）矩阵（其中，n和m为1以上的整数）等间隔配置的岛状栅极绝缘层，以及栅电极 第一高度（t1）放置在衬底的阱区域中的栅极绝缘层上; 接触栅电极的栅极接触; 电连接到栅极触点的第二高度（t2）（其中，t1