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公开(公告)号：USRE40552E1
公开(公告)日：2008-10-28
申请号：US10032431
申请日：2001-12-21
IPC分类号： G11C7/00
CPC分类号： G11C7/00
摘要： Apparatus and methods for controlling the sensing of bit lines which facilitates the distribution of bit line charging current to be distributed any time, and facilitates the fast raising of the sense modes to full logic levels. An embodiment is comprised of a plurality of bit storage capacitors, a folded bit line for receiving charge stored on one of the capacitors, having bit line capacitance, a sense amplifier having a pair of sense nodes for sensing a voltage differential across the sense nodes, apparatus connected to the bit line and the sense nodes for imperfectly isolating the sense nodes from the bit line whereby current can leak therethrough, apparatus for enabling the sense amplifier and for disabling the isolating apparatus and thereby removing the isolation between the sense amplifier and the bit line, whereby current passing through the sense amplifier to the sense nodes is enabled to charge the bit line capacitance through the isolating apparatus to predetermined logic voltage level.
摘要翻译： 用于控制位线感测的装置和方法，其有助于随时分布的位线充电电流的分布，并且有助于将感测模式快速升高到完全逻辑电平。 一个实施例包括多个位存储电容器，用于接收存储在其中一个电容器上的电荷的折叠位线，具有位线电容，读出放大器具有用于感测跨感测节点的电压差的一对感测节点， 连接到位线的装置和感测节点，用于使感测节点与位线不完全隔离，由此电流可以泄漏，用于使读出放大器和禁用隔离装置的装置，从而消除读出放大器和位之间的隔离 从而使通过感测放大器的电流到感测节点能够通过隔离装置将位线电容充电到预定的逻辑电压电平。
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公开(公告)号：USRE37641E1
公开(公告)日：2002-04-09
申请号：US08853507
申请日：1997-05-08
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C11/4091 , G11C11/4094
摘要： Apparatus and methods for controlling the sensing of bit lines which facilitates the distribution of bit line charging current to be distributed any time, and facilitates the fast raising of the sense modes to full logic levels. An embodiment is comprised of a plurality of bit storage capacitors, a folded bit line for receiving charge stored on one of the capacitors, having bit line capacitance, a sense amplifier having a pair of sense nodes for sensing a voltage differential across the sense nodes, apparatus connected to the bit line and the sense nodes for imperfectly isolating the sense nodes from the bit line whereby current can leak therethrough, apparatus for enabling the sense amplifier and for disabling the isolating apparatus and thereby removing the isolation between the sense amplifier and the bit line, whereby current passing through the sense amplifier to the sense noes is enabled to charge the bit line capacitance through the isolating apparatus to predetermined logic voltage level.
摘要翻译： 用于控制位线感测的装置和方法，其有助于随时分布的位线充电电流的分布，并且有助于将感测模式快速升高到完全逻辑电平。 一个实施例包括多个位存储电容器，用于接收存储在其中一个电容器上的电荷的折叠位线，具有位线电容，读出放大器具有用于感测跨感测节点的电压差的一对感测节点， 连接到位线的装置和感测节点，用于使感测节点与位线不完全隔离，由此电流可以泄漏，用于使读出放大器和禁用隔离装置的装置，从而消除读出放大器和位之间的隔离 线路，由此使通过感测放大器的电流到感测位置能够通过隔离装置将位线电容充电到预定的逻辑电压电平。
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公开(公告)号：US5574681A
公开(公告)日：1996-11-12
申请号：US377622
申请日：1995-01-25
IPC分类号： G11C7/12 , G11C11/4091 , G11C11/4094 , G11C7/00
CPC分类号： G11C7/12 , G11C11/4091 , G11C11/4094
摘要： A DRAM having a plurality of bit lines and associated sense amplifiers, the bit lines being arrayed across an integrated circuit chip and the sense amplifiers being disposed in a row, a pair of low resistance power supply conductors extending in parallel with the row for carrying logic high level and logic low level voltages, sense amplifier enabling signal conductors extending across the chip accessible to the sense amplifiers, apparatus for coupling sense inputs of the sense amplifiers to the power supply conductors, and apparatus coupling the sense amplifier enabling signal conductors to the apparatus for coupling sense inputs, for enabling passage of current resulting from the logic high level and low level voltages to the sense amplifiers.
摘要翻译： 具有多个位线和相关读出放大器的DRAM，位线横跨集成电路芯片排列，读出放大器布置成一行，一对与该行并行延伸的低电阻电源导体，用于承载逻辑 高电平和逻辑低电平电压，读出放大器使得能够在读出放大器可访问的芯片上延伸的信号导体，用于将感测放大器的感测输入耦合到电源导体的装置，以及将感测放大器使能信号导体耦合到装置 用于耦合感测输入，用于使由逻辑高电平和低电平电压产生的电流能够通过感测放大器。
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公开(公告)号：US5414662A
公开(公告)日：1995-05-09
申请号：US147038
申请日：1993-11-04
IPC分类号： G11C7/12 , G11C11/4091 , G11C11/4094 , G11C7/02
CPC分类号： G11C7/12 , G11C11/4091 , G11C11/4094
摘要： Apparatus and methods for controlling the sensing of bit lines which facilitates the distribution of bit line charging current to be distributed any time, and facilitates the fast raising of the sense modes to full logic levels. An embodiment is comprised of a plurality of bit storage capacitors, a folded bit line for receiving charge stored on one of the capacitors, having bit line capacitance, a sense amplifier having a pair of sense nodes for sensing a voltage differential across the sense nodes, apparatus connected to the bit line and the sense nodes for imperfectly isolating the sense nodes from the bit line whereby current can leak therethrough, apparatus for enabling the sense amplifier and for disabling the isolating apparatus and thereby removing the isolation between the sense amplifier and the bit line, whereby current passing through the sense amplifier to the sense nodes is enabled to charge the bit line capacitance through the isolating apparatus to predetermined logic voltage level.
摘要翻译： 用于控制位线感测的装置和方法，其有助于随时分布的位线充电电流的分布，并且有助于将感测模式快速升高到完全逻辑电平。 一个实施例包括多个位存储电容器，用于接收存储在其中一个电容器上的电荷的折叠位线，具有位线电容，读出放大器具有用于感测跨感测节点的电压差的一对感测节点， 连接到位线的装置和感测节点，用于使感测节点与位线不完全隔离，由此电流可以泄漏，用于使读出放大器和禁用隔离装置的装置，从而消除读出放大器和位之间的隔离 从而使通过感测放大器的电流到感测节点能够通过隔离装置将位线电容充电到预定的逻辑电压电平。
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5.发明授权Delay locked loop implementation in a synchronous dynamic random access memory 失效在同步动态随机存取存储器中延迟锁定环路的实现公开(公告)号：US08369182B2
公开(公告)日：2013-02-05
申请号：US12547955
申请日：2009-08-26
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1072 , G11C7/22 , G11C7/222 , H03K5/133 , H03L7/0814
摘要： A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
摘要翻译： 用于同步存储器的时钟施加电路包括用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置和用于接收用于传送时钟驱动的时钟输入信号的抽头延迟线 与时钟输入信号同步但延迟到同步存储器，延迟是时钟输入信号的时钟周期的一小部分。
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公开(公告)号：US06657919B2
公开(公告)日：2003-12-02
申请号：US10348062
申请日：2003-01-17
IPC分类号： G11C800
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1072 , G11C7/22 , G11C7/222 , H03K5/133 , H03L7/0814
摘要： A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
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公开(公告)号：US06205083B1
公开(公告)日：2001-03-20
申请号：US09392088
申请日：1999-09-08
IPC分类号： G11C800
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1072 , G11C7/22 , G11C7/222 , H03K5/133 , H03L7/0814
摘要： A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
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公开(公告)号：US5796673A
公开(公告)日：1998-08-18
申请号：US319042
申请日：1994-10-06
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1072 , G11C7/22 , G11C7/222 , H03K5/133 , H03L7/0814
摘要： A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
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公开(公告)号：US06614705B2
公开(公告)日：2003-09-02
申请号：US09819488
申请日：2001-03-28
IPC分类号： G11C800
CPC分类号： G11C5/145 , G05F3/205 , G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/4085 , H02M3/07
摘要： A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.
摘要翻译： 用于提供用于DRAM字线的输出电压的电路，其可用于驱动可高达2Vdd的存储器字线。 升压电路中的晶体管完全切换，消除了Vtn通过晶体管降低升压电压。 升压电容器由Vdd充电。 调节器检测存储单元存取晶体管的复制品的传导电流，当达到操作存取晶体管的正确电压时，切断升压电路时钟振荡器。
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10.发明申请Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory 失效在同步动态随机存取存储器中实现延迟锁定环公开(公告)号：US20090316514A1
公开(公告)日：2009-12-24
申请号：US12547955
申请日：2009-08-26
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1072 , G11C7/22 , G11C7/222 , H03K5/133 , H03L7/0814
摘要： A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
摘要翻译： 用于同步存储器的时钟施加电路包括用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置和用于接收用于传送时钟驱动的时钟输入信号的抽头延迟线 与时钟输入信号同步但延迟到同步存储器，延迟是时钟输入信号的时钟周期的一小部分。
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